AN2556

Modified features

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1.8.2

Software impacts

Parts related to the initialization of the POCONx registers should be suppressed.

1.9

PLL and on-chip main oscillator

Compared to the ST10F269Zx, several modifications have been introduced:

●

PLL multiplication factors have been adapted in order to match the new frequency range.

●

On-chip main oscillator input frequency range has been reshaped, reducing it to 4 to12 MHz. This

allows a power consumption reduction when the Real Time Clock is running in Power Down mode

using as a reference the on-chip main oscillator clock.

●

When the PLL is used, the CPU frequency range is 16 to 64 MHz.

Figure 1.: ST10F273Z4 clock generation diagram gives a simplified overview of the CPU clock

generation. Values will be set for each stage depending on the multiplication factor selected via Port0 at

reset. The CPU clock is in fact generated mainly from a VCO with the following characteristics:

●

Input range: 1 to 3.5 MHz, which explains the Prescaler that divides the XTAL frequency

●

Output range: 64 to 128 MHz which is then divided through Divider1 to generate the CPU clock

Figure 1.

ST10F273Z4 clock generation diagram

Table 11.: ST10F269Zx vs. ST10F273Z4 PLL ratio lists the new PLL multiplications factors

and the corresponding frequency ranges for the ST10F273Z4.

Fxtal

Phase Comparator

Prescaler

VCO

Divider 1

Divider 2

Fcpu

ai13310

Table 11.

P0.15-13

(P0H.7-5)

PLL multiplication factor

ST10F273Z4 oscillator

ST10F269Zx

ST10F273Z4

Input range (MHz)

CPU clock range (MHz)

1

1

1

* 4

* 4

4 to 8

16 to 32

1

1

0

* 3

* 3

5.34 to 10.66

16.02 to 32

1

0

1

* 2

* 8

4 to 8

32 to 64

1

0

0

* 5

* 5

6.4 to 12

32 to 60

0

1

1

* 1

* 1

1 to 64

10 to 64