Modified features

AN2556

18/35

1.9.1

Hardware impacts

The Port0 configuration may be changed with regard to the new PLL factor.

The component on XTAL1 & XTAL2 (Crystal and capacitors, or resonator) must be changed

for the following reasons:

●

The input frequency range is now reduced.

●

It is no longer possible to use a crystal or a ceramic resonator in Direct Drive mode.

●

It is no longer possible to use a PLL factor with a frequency generator.

●

The electrical characteristics of the main oscillator have changed (transconductance)

1.9.2

Software impacts

None.

0

1

0

* 1.5

* 10

4 to 6.4

40 to 64

0

0

1

* 0.5

* 0.5

4 to 12

2 to 6

0

0

0

* 2.5

* 16

4

64

1.

All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal

oscillator amplifier, except the Direct Drive mode (oscillator amplifier disabled, so no crystal or resonator

can be used). Vice versa, the clock can be forced through an external clock source only in Direct Drive

mode.

Table 11.

P0.15-13

(P0H.7-5)

PLL multiplication factor

ST10F273Z4 oscillator

ST10F269Zx

ST10F273Z4

Input range (MHz)

CPU clock range (MHz)