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AN2556 Datasheet(PDF) 24 Page - STMicroelectronics |
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AN2556 Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 35 page ![]() Modified registers AN2556 24/35 3 Modified registers 3.1 XPERCON register In ST10F273Z4, new bits have been added with regard to the additional X-Peripherals. The XPERCON register allows the X-Bus peripherals to be separately selected so they are visible to the user by means of corresponding bits. If not selected (not activated with a bit of XPERCON) before the XPEN bit in SYSCON is set, the corresponding address space, port pins and interrupts are not occupied by the peripheral, and thus this peripheral is not visible and not available. ST10F269Zx: XPERCON (F024h/12h) SFR Reset value: --05h 15 14 13 12 11 10 9876 5 4321 0 Reserved RTC EN XRAM 2EN XRAM 1EN CAN2 EN CAN1 EN - RW RW RWRWRW ST10F273Z4: XPERCON (F024h/12h) SFR Reset value: -005h 15 14 13 12 11 10 9876 5 4321 0 Reserved XMIS CEN X12 CEN XSSC EN XAS CEN XPW MEN XFLA SHEN RTC EN XRAM 2EN XRAM 1EN CAN2 EN CAN1 EN - RWRW RW RWRWRW RW RW RW RW RW Table 15. XPERCON register description Bit Bit name Function 0CAN1EN CAN1 Enable Bit 0: Accesses the CAN1 XPeripheral and its functions are disabled (P4.5 and P4.6 pins can be used as general purpose I/Os). 1: The CAN1 XPeripheral is enabled and can be accessed. 1CAN2EN CAN2 Enable Bit 0: Accesses the CAN2 XPeripheral and its functions are disabled (P4.4 and P4.7 pins can be used as general purpose I/Os). 1: The CAN2 XPeripheral is enabled and can be accessed. 2XRAM1EN XRAM1 Enable Bit 0: Access to the XRAM1 block is disabled, external access performed. 1: The on-chip XRAM1 is enabled and can be assessed 3XRAM2EN XRAM2 Enable Bit 0: Access to the XRAM2 block is disabled, external access performed. 1: The on-chip XRAM2 is enabled and can be assessed. 4RTCEN RTC Enable Bit 0: Access to the Real Time Clock is disabled, external access performed. 1: The Real Time Clock is enabled and can be accessed. |
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