UPD70741 datasheet(32/112 Pages) NEC

32 / 112 page

µPD70741

6. MEMORY ACCESS CONTROL FUNCTIONS

6.1 DRAM Controller (DRAMC)

The DRAM controller (DRAMC) generates the REFRQ, RAS, LCAS, and UCAS signals, and controls access to

DRAM. Access to DRAM is achieved by multiplexing the DRAM row and column addresses and outputting them from

the address pins.

The microprocessor assumes the connected DRAM to be of

× 4 bits or more, and that it supports high-speed page

mode. There are two types of DRAM access cycles, on-page (2 or 3 clock pulses) and off-page (4 or 5 pulses).

Refresh uses the CAS before RAS method, allowing the user to set any refresh period. In IDLE and STOP modes,

CBR self-refresh is performed.

6.1.1 Features

• Generates the REFRQ, RAS, LCAS, and UCAS signals.

• Supports DRAM high-speed page mode.

• Address multiplexing function: 8, 9, 10, and 11 bits

• CBR refresh and CBR self-refresh functions

6.1.2 Address multiplexing function

In the DRAM cycle, row and column addresses are multiplexed according to the value of the DAW bits of the DRAM

configuration register (DRC), then output, as shown in Figure 6-1. In Figure 6-1, a0-a23 are the addresses output

from the CPU, while A0-A23 are the address pins of the V821. For example, if DAW = 11, row address a12-a22 and

column address a1-a11 are output from address pins (A1-A11).

Table 6-1 lists the relationship between the connectable DRAMs and address multiplexing widths. Depending on

the connected DRAM, the DRAM space can be between 128 Kbytes and 8 Mbytes.

Figure 6-1. Output of Row and Column Addresses

a23

a16

a15 a14 a13 a23

a22

a21 a20

a19 a18

a17 a16

a15 a14

a13 a12 a11

A23

A16

A15 A14 A13 A12 A11 A10 A9

a23

a16

a15 a14 a23 a22

a21

a20 a19

a18 a17

a16 a15

a14 a13

a12 a11 a10

a23

a16

a15 a23 a22 a21

a20

a19 a18

a17 a16

a15 a14

a13 a12

a11 a10

a23

a16

a23 a22 a21 a20

a19

a18 a17

a16 a15

a14 a13

a12 a11

a10

a23

Address pin

Row address

DAW = 11

DAW = 10

DAW = 01

DAW = 00

Column address

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