UPD70741 datasheet(47/112 Pages) NEC

47 / 112 page

µPD70741

13. STANDBY FUNCTIONS

The V821 supports three standby modes to suppress power dissipation. In these standby modes, the operation

of the clock is controlled. The HALT instruction is used to select a standby mode. Mode switching is controlled using

the standby control register.

13.1 Features

HALT mode (Only the CPU clock stops.)

IDLE mode (The CPU and peripheral operation clocks stop. The clock generator continues to operate.)

STOP mode (The entire system, including the clock generator, stops.)

13.2 Standby Mode

The standby modes of the V821 are detailed below.

(1) HALT mode

In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but the CPU clock stops.

Clock supply to other built-in peripheral functions continues to allow them to keep running. Intermittent operation

achieved using this standby mode in conjunction with the ordinary operation mode can reduce the total power

dissipation of the system.

(2) IDLE mode

In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but internal system clock

supply is stopped to bring the entire system to a stop.

When the system is released from IDLE mode, it is unnecessary to secure oscillation settling time for the oscillator,

and therefore it is possible for the system to shift to the ordinary operation quickly.

For the oscillation settling time and current drain, IDLE mode lies in between STOP and HALT modes. IDLE

mode is suitable for an application where it is necessary to cut the oscillation settling time using a low current

drain mode.

(3) STOP mode

In this mode, the clock generator (oscillator and PLL synthesizer) is stopped to bring the entire system to a stop.

This mode can generate an ultra-low power dissipation condition; only leak current occurs.

(a) PLL mode

In this mode, the PLL synthesizer clock output is stopped simultaneously with the oscillator. After the

system is released from STOP mode, it is necessary to allow oscillation settling time for the oscillator.

Some programs require a PLL lock-up time.

(b) Direct mode

In the direct mode, it is unnecessary to secure lock-up time.

Table 13-1 lists the operation of the clock generator in the ordinary, HALT, IDLE, and STOP modes. An effective

low power dissipation system can be implemented by combining and switching these modes.

UPD70741 Datasheet(PDF) 47 Page - NEC