UPD70741 datasheet(76/112 Pages) NEC

76 / 112 page

µPD70741

(5) DRAM access timing (when DRAM is directly connected)

(a) Read timing (normal access: off-page) (1/2)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Delay from RD

↑ to write data output (ADC = 0)

tDRD0

0.5T - 10

Delay from RD

↑ to write data output (ADC = 1)

tDRD1

1T - 10

Read/write cycle time

tRC

(w + 4)T - 10

RAS access time

tRAC

(w + 2)T - 20

CAS access time

tCAC

(w + 1)T - 20

Access time from column address

tAA

(w + 1)T - 3

Output enable access time

tOEA

1.5T - 20

Output buffer turn-off delay (relative to CAS)

tOFF

0ns

Output buffer turn-off delay (relative to MRD)

tOEZ

0ns

RD setup time (relative to RAS

↑)

tOES

1.5T

RAS precharge time

tRP

1.5T - 10

RAS pulse width

tRAS

(w + 2.5)T - 20

RAS column address delay

tRAD

0.5T - 3

0.5T + 7

RAS hold width (read)

tRSH

(w + 1.5)T - 20

CAS pulse width (read)

tCAS

(w + 1)T - 15

CAS hold width

tCSH

(w + 2)T - 15

RAS-CAS delay (read)

tRCD

1T - 15

RAS-CAS precharge time

tCRP

1.5T

CAS precharge time

tCP

0.5T - 10

Row address setup time

tASR

0.5T - 15

Row address hold time

tRAH

0.5T - 7

Column address setup time (read)

tASC

0.5T - 15

Column address hold time (read)

tCAH

(w + 1)T - 15

Column address read time relative to RAS

tRAL

(w + 1.5)T

Read command setup time

tRCS

0.5T

Read command hold time

tRCH

0.5T - 15

Remark T: tCYK

w : Wait state count - 2

UPD70741 Datasheet(PDF) 76 Page - NEC

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