Video Imaging Products

13

LF3370

High-Definition Video Format Converter

03/13/2001–LDS.3370-F

DEVICES INCORPORATED

LD is used to enable and disable the

LF Interface™. WhenLDgoesLOW,the

LF Interface™isenabledfordatainput.

The first value fed into the interface on

what the interface is going to load (see

Table 4). For example, to load address

Bias Adder Register 2 of the channel B

Output Bias Adder, the first data value

intotheLFInterface™shouldbe0A02H.

To load RSL Register 1 for the Keyscaler

RSL, the first data value should be 1101H.

The first address value should be loaded

into the interface on the same clock cycle

that latches the HIGH to LOW transition

of LD. The next value(s) loaded into the

interface are the data value(s) which will

be stored in the bank or register defined

by the address value. When loading

coefficient banks, the interface will expect

ten values to be loaded into the device

after the address value. The ten values are

coefficients 0 through 8 and the Keyscale

coefficient. When loading Configuration

or Bias Registers, the interface will expect

one value after the address value. When

loading RSL registers, the interface will

DESCRIPTION

ADDRESS RANGE (HEX)

Coefficient Registers

0000 - 0003

Configuration Registers

0200 - 020A

Look-Up Table - Channel ‘A’

0300

Look-Up Table - Channel ‘B’

0400

Look-Up Table - Channel ‘C’

0500

Input Bias Registers - Channel ‘A’

0600 - 0603

Input Bias Registers - Channel ‘B’

0700 - 0703

Input Bias Registers - Channel ‘C’

0800 - 0803

Output Bias Registers - Channel ‘A’

0900 - 0903

Output Bias Registers - Channel ‘B’

0A00 - 0A03

Output Bias Registers - Channel ‘C’

0B00 - 0B03

HF0 Count Value

0C00

HF1 Count Value

0D00

Matrix Mult. RSL Registers - Channel ‘A’

0E00 - 0E03

Matrix Mult. RSL Registers - Channel ‘B’

0F00 - 0F03

Matrix Mult. RSL Registers - Channel ‘C’

1000 - 1003

Key Scaler RSL Registers

1100 - 1103

Half-Band Filter RSL Registers - Channel ‘B’

1200 - 1203

Half-Band Filter RSL Registers - Channel ‘C’

1300 - 1303

VARIABLE LENGTH

BYPASS DELAY

(127 x 13-Bit )

HALF-BAND

FILTER

SECTION

MATRIX MULTIPLIER

and KEY SCALER

SECTION

LUT

SECTION

OUTPUT

BIAS

SECTION

VARIABLE LENGTH

BYPASS DELAY

(127 x 13-Bit )

INPUT

BIAS

SECTION

13

INPUT

DEMUX

SECTION

13

OUTPUT

MUX

SECTION

13

LUT

SECTION

A,

B,

C,

D

W,

X,

Y,

Z

13

In this example, the Matrix-Multipler/Key Scaler Section feeds the Half-Band Filter Section. This arrangement is reversible.

CLK

In this example, the Output Multiplexer is in a mode where the delay through the section is 2 CLK cycles. Only one channel is shown in this example,

however, the other three channels behave in the same manner. The example assumes that the bypass RAM length is set to the length of the core data path.

Core Data

*

Output*

DATAPASS

Bypass Data

W1: Bypass data is output to the output port and replaces core data.

W2: Core data is output to the output port and replaces bypass data.

W1

W2