Video Imaging Products

5

LF3370

High-Definition Video Format Converter

03/13/2001–LDS.3370-F

DEVICES INCORPORATED

on the rising edge of CLK.

RESET — Reset

RESET is used to reset all program-

mable flags and line up clock edges

during single muxed input or single

muxed output events. RESET is used

at power up or just after device

the rising edge of CLK.

LF3370DeviceInitialization

This section explains how to initialize the

deviceforproperoperation. Italsoservesas

a summary of all conditions that should be

consideredbeforeusingthedeviceorfor

troubleshooting.

ConfigurationRegister0andConfiguration

Register1mustbeloadedbeforeoperation

ofthedevice. IfCoreBypassingisdesired,

ConfigurationRegister2mustbeloaded

beforeuse. IfuseoftheHalf-BandFiltersis

desired,atleastoneHalf-BandFilterRSL

RegisterSetmustbeloadedandselectedfor

eachHalf-BandFilter.

IfuseoftheMatrixMultiplier/KeyScaleris

desired,atleastoneMatrixMultiplier/Key

ScalerRSLRegisterSetandcoefficient

address mustbeloadedandselectedfor

each channel. If use of the Input Bias Adder

is desired, at least one Input Bias Adder

Registermustbeloadedandselectedbefore

use. IfuseoftheOutputBiasAdderis

desired,atleastoneOutputBiasAdder

Registermustbeloadedandselectedbefore

use. IfuseoftheLook-UpTableisdesired,

theLook-UpTablemustbeloadedbefore

use.

When using a single channel input or

output with interleaved video, SYNC and

RESET should be used for proper initializa-

tion as shown in Figure 5. If 12 bits or less

input data is desired, the input data should

be shifted so the MSBs are aligned.

Input Demultiplexer

The input demultiplexer section acts as a

buffer between the user’s datapath and the

* Not all input/output combinations are valid. If single channel interleaved video

is used on either the input or output, the core clock will be running at CLK/2.

Thus the maximum input, output, and core data rate must be considered.

Input

Input Format*

Channel

4:4:4:4

4:2:2:4

4:2:2:4

4:2:2:4

R

Y

Y

Y/Cb/Cr

G

Cb

Cb/Cr

N/A

B

Cr

N/A

N/A

Key

Key

Key

Key

Output

Output Format*

Channel

4:4:4:4

4:2:2:4

4:2:2:4

4:2:2:4

R

Y

Y

Y/Cb/Cr

G

Cb

Cb/Cr

N/A

B

Cr

N/A

N/A

Key

Key

Key

Key

12 11 10

2

1

0

–2

0

(Sign)

2

2

Coefficient Data

12 11 10

2

1

0

–2

12

(Sign)

2

2

2

2

1

2

0

12 11 10

2

1

0

–2

12

(Sign)

2

2

2

2

1

2

0

Input Data

Output Data

INPUT BIAS ADDER/OUTPUT BIAS ADDER

MATRIX MULTIPLIER/KEY SCALER

–2

15

(Sign)

2

2

–2

13

(Sign)

2

2

*Matrix Multiplier Output

*Key Scaler Output

12 11 10

2

1

0

–2

12

(Sign)

2

2

2

2

1

2

0

Input Data

HALF-BAND FILTER

**Filter Output (Non-Interpolate)

**Filter Output (Interpolate)

12 11 10

2

1

0

–2

12

(Sign)

2

2

2

2

1

2

0

Input Data

–2

12

(Sign)

2

2

–2

13

(Sign)

2

2