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DS_FT600Q-FT601Q IC Datasheet/FT601 USB 3.0 to FIFO Bridge

Version 1.01

Document No.: FT_001118 Clearance No.: FTDI#424

The waveform below shows a master read transaction for 12 valid bytes at channel 1, where the bus

master terminates the transaction. There are turn-a-round cycles for DATA[7:0], DATA[31:16] and

BE[3:0] after the command phase and at the end of the data transaction.

* The data is valid when WR_N and RXF_N are both active.

Figure 4.2 Multi-Channel FIFO mode master read transaction 2

⃰In Multi-channel FIFO mode master read operation, the bus master shall be able to read out the

maximum possible data in the RX FIFO in one read transaction, i.e. when the FT600 or FT601 is

configured in the 1 channel Multi-channel FIFO mode, the bus master shall be able to read out 4 KB in

if the bus master expects the data to be transferred over USB bus in the maximum possible packet length, it

should write the data to the FIFO in a single bus transaction.

E.g. in a USB 3.0 super-speed connection with a packet size is 1 KB, and a FIFO size of 4 KB, if the bus

master completes the 4 KB in one transaction then the data will be transferred on the USB bus in 4 full

sized packets. If the bus master completes 1 KB in one transaction, the data will be transferred on the USB

bus in 1 packet. If the bus master completes 1025 bytes in one transaction, the data will be transferred

over USB in 1 full sized packet and one short packet with 1 byte.

The waveform below shows a master write transaction for 14 bytes at channel 1 with the bus master

terminating the transaction. There are turn-a-round cycles for DATA[15:8] after the command phase and

at the end of the data transaction. The BE[3:0] shows that the lower 2 bytes in D3 are valid at the last

word strobe in this transaction.

Figure 4.3 Multi-Channel FIFO mode master write transaction 1

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