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FT600 Datasheet(PDF) 8 Page - Future Technology Devices International Ltd. |
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FT600 Datasheet(HTML) 8 Page - Future Technology Devices International Ltd. |
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8 / 29 page ![]() Copyright © 2015 Future Technology Devices International Limited 8 DS_FT600Q-FT601Q IC Datasheet/FT601 USB 3.0 to FIFO Bridge Version 1.01 Document No.: FT_001118 Clearance No.: FTDI#424 WAKEUP_N Suspend/Remote Wakeup pin. Active low. I 16 11 Reserved Do not connect. I/O 19 14 GPIO0 Configurable GPIO port0. I/O 17 12 GPIO1 Configurable GPIO port1. I/O 18 13 VBUS USB BUS power input. I 37 29 XI Crystal input. This terminal is the crystal input for the internal oscillator. I 21 16 XO Crystal Output. This terminal is the crystal output for the internal oscillator. O 22 17 DP High-speed USB differential transceiver (positive) I/O 23 18 DM High-speed USB differential transceiver (negative) I/O 25 20 RREF PHY reference resistor input pin. Connect 1.6K Ω 1% resistor to ground, provides reference voltage to USB2 PHY. I 27 21 TODN Super Speed USB transmitter differential pair (negative) O 31 24 TODP Super Speed USB transmitter differential pair (positive) O 32 25 RIDN Super Speed USB receiver differential pair (negative) I 34 27 RIDP Super Speed USB receiver differential pair (positive) I 35 28 VCC33 +3.3V power input for chip and internal LDO. PWR 20,24, 38 15,19, 30 DV10 +1.0V power output from internal LDO. Connecting to VD10 and AVDD, with a 4.7uF cap to ground is recommended. O 39 31 VD10 +1.0V core voltage input. PWR 3,30,3 3,48 23,26, 37,50 VCCIO Power input for I/O block, supports +1.8/+2.5/+3.3V. PWR 14,49, 59,68 38,44, 52 VDDA +3.3V power input for USB2.0 and USB3.0 PHYs. PWR 28 22 AVDD +1.0V power input for PLL. PWR 2 1 GND Ground GND 1,26, 29,36 32, 49,51 Table 3.1 Device pin out Signal descriptions |
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