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DS_FT600Q-FT601Q IC Datasheet/FT601 USB 3.0 to FIFO Bridge

Version 1.01

Document No.: FT_001118 Clearance No.: FTDI#424

4.4 FIFO Bus AC timing

The FT600/FT601 device FIFO bus is a synchronous parallel bus. The CLK signal is generated by the

device, with the typical FIFO clock duty cycle of 50%. Both Multi-Channel and 245 synchronous FIFO

modes’ worst case AC timing are shown in Figure 4.7 and Table 4.2.

In this figure, ‘Input Data’ includes all control signals and data lines driven by the FIFO master. ‘Output

Data’ includes all control signals and data lines driven by the FIFO slave - FT600/FT601 .

Figure 4.8 FIFO Bus AC timing diagram

Time

Description

Minimum

Maximum Unit

T1

Slave Drive Data Set Up Time

3.0

-

ns

T2

Slave Drive Data Hold Time

3.5

-

ns

T3

Master Drive Data Set Up Time

2.3

-

ns

T4

Master Drive Date Hold Time

3.8

-

ns

Table 4.2 FIFO Bus AC timing

CLK

Output Data

T1

Input Data

T2

T3

T4