SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

S-1721 Series

Seiko Instruments Inc.

18

Standard Circuit

*1.

*2.

A ceramic capacitor of 1.0

μF or more can be used for C

VOUT1

ON/OFF1

ON/OFF2

GND

VIN

VOUT2

Single GND

OUTPUT 1

INPUT

VSS

OUTPUT 2

*2

*2

*1

Figure

21

Caution

The above connection diagram and constant will not guarantee successful operation. Perform

thorough evaluation using the actual application to set the constant.

Condition of Application

1.0

μF or more

1.0

μF or more (ceramic capacitor)

Caution A general series regulator may oscillate, depending on the external components. Confirm that no

oscillation occurs in the application for which the above capacitors are used.

The S-1721 Series requires an output capacitor between the VOUT and VSS pin for phase compensation. Operation is

stabilized by a ceramic capacitor with an output capacitance of 1.0

μF or more over the entire temperature range.

When using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, the capacitance must be 1.0

μF or

more.

The value of the output overshoot or undershoot transient response varies depending on the value of the output

capacitor. The required capacitance of the input capacitor differs depending on the application.

the output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual

device.