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AM5728 Datasheet(PDF) 270 Page - Texas Instruments

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Part # AM5728
Description  AM572x SitaraTM Processors
PDF  415 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM5728 Datasheet(HTML) 270 Page - Texas Instruments

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1-WIRE
Vayu_HDQ1W_05
t
RTSL
t
PDH
t
PDL
t
RSTH
HDQ
Break
0_(LSB)
1
6
7_(MSB)
t
RSPS
1
6
Command_byte_written
Data_byte_received
0_(LSB)
Vayu_HDQ1W_04
HDQ
Vayu_HDQ1W_03
t
CYCD
t
DW0
t
DW1
AM5728, AM5726
SPRS915O – MARCH 2014 – REVISED OCTOBER 2015
www.ti.com
Figure 7-27. Device HDQ Interface Bit Write Timing (Command / Address or Data)
Figure 7-28. HDQ Communication Timing
7.13.2 HDQ/1-Wire—1-Wire Mode
Table 7-38 and Table 7-39 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-29, Figure 7-30, and Figure 7-31).
Table 7-38. HDQ / 1-Wire Timing Requirements - 1-Wire Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
10
tPDH
Presence pulse delay high
15
60
µs
11
tPDL
Presence pulse delay low
60
240
µs
12
tRDV
Read data valid time
tLOWR
15
µs
13
tREL
Read data release time
0
45
µs
Table 7-39. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
14
tRSTL
Reset time low
480
960
µs
15
tRSTH
Reset time high
480
µs
16
tSLOT
Bit cycle time
60
120
µs
17
tLOW1
Write bit-one time
1
15
µs
18
tLOW0
Write bit-zero time(2)
60
120
µs
19
tREC
Recovery time
1
µs
20
tLOWR
Read bit strobe time(1)
1
15
µs
(1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.
(2) tLOW0 must be less than tSLOT.
Figure 7-29. 1-Wire—Break (Reset)
270
Timing Requirements and Switching Characteristics
Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: AM5728 AM5726



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