AM5728 datasheet(271/415 Pages) TI

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1-WIRE

Vayu_HDQ1W_07

LOW1

LOW0

_and t

SOT

REC

1-WIRE

LOWR

and_

RDV_

REL

_and_

SLOT

REC

Vayu_HDQ1W_06

AM5728, AM5726

www.ti.com

SPRS915O – MARCH 2014 – REVISED OCTOBER 2015

Figure 7-30. 1-Wire—Read Bit (Data)

Figure 7-31. 1-Wire—Write Bit-One Timing (Command / Address or Data)

7.14 Universal Asynchronous Receiver Transmitter (UART)

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-

to-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one

UART supports IrDA features. Each UART can be used for configuration and data exchange with a

number of external peripheral devices or interprocessor communication between devices

The UARTi (where i = 1 to 10) include the following features:

•

16C750 compatibility

•

64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter

•

Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed

functional clock of 48 MHz or 192 MHz

•

Break character detection and generation

•

Configurable data format:

–

Data bit: 5, 6, 7, or 8 bits

–

Parity bit: Even, odd, none

–

Stop-bit: 1, 1.5, 2 bit(s)

•

Flow control: Hardware (RTS/CTS) or software (XON/XOFF)

•

Only UART1 module has extended modem control signals (DCD, RI, DTR, DSR)

•

Only UART3 supports IrDA

NOTE

For more information, see the UART/IrDA/CIR section of the Device TRM.

Table 7-40, Table 7-41 and Figure 7-32 assume testing over the recommended operating conditions and

electrical characteristic conditions below.

Table 7-40. Timing Requirements for UART

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tw(RX)

Pulse width, receive data bit, 15/30/100pF high or low

0.96U(1)

1.05U(1)

tw(CTS)

Pulse width, receive start bit, 15/30/100pF high or low

0.96U(1)

1.05U(1)

td(RTS-TX)

Delay time, transmit start bit to transmit data

P(2)

td(CTS-TX)

Delay time, receive start bit to transmit data

P(2)

Timing Requirements and Switching Characteristics

271

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