LP38859 datasheet(12/25 Pages) TI

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LP38859

SNVS337F – JUNE 2006 – REVISED SEPTEMBER 2015

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Feature Description (continued)

Because VREF appears on the SS pin, any leakage through CSS causes VREF to fall, and thus affect VOUT. A

leakage of 50 nA (about 10 M

Ω) through CSS causes VOUT to be approximately 0.1% lower than nominal, while a

leakage of 500 nA (about 1 M

Ω) causes VOUT to be approximately 1% lower than nominal. Typical ceramic

capacitors have a factor of 10× difference in leakage between 25°C and 85°C, so the maximum ambient

temperature must be included in the capacitor selection process.

Typical CSS values are in the range of 1 nF to 100 nF, providing typical soft-start times in the range of 70 μs to 7

ms (5

τ). Values less than 1 nF can be used, but the soft-start effect is minimal. Values larger than 100 nF

provide soft start, but may not be fully discharged if VBIAS falls from the UVLO threshold to less than 500 mV in

less than 100 µs.

Figure 19 shows the relationship between the COUT value and a typical CSS value.

Figure 19. Typical CSS vs COUT Values

The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components,

other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT.

If the soft-start function is not needed, the SS pin must be left open, although some minimal capacitance value is

always recommended.

7.4 Device Functional Modes

7.4.1 Operation with 3 V

≤ VBIAS ≤ 5.5 V, VOUT(TARGET)+ 0.3 V ≤ VIN ≤ VBIAS

The device operates if the bias voltage is equal to, or exceeds, 3 V, and input voltage is equal to, or exceeds,

VOUT(TARGET) + 0.3 V. At bias voltages below the minimum VBIAS requirement, the device does not operate

correctly, and output voltage may not reach target value.

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LP38859 Datasheet(PDF) 12 Page - Texas Instruments