LP38859 datasheet(17/25 Pages) TI

17 / 25 page

GND

OUT

VIN

VOUT

COUT

CIN

BIAS

CSS

CBIAS

LP38859

www.ti.com

SNVS337F – JUNE 2006 – REVISED SEPTEMBER 2015

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP38859 is dependent on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP38859. Best

performance is achieved by placing CIN and COUT on the same side of the PCB as the LP38859, and as close as

is practical to the package. The ground connections for CIN and COUT must be back to the LP38859 ground pin

using as wide and short of a copper trace as is practical.

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.

The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP38859 using

traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND

pins. The regulator ground pin must be connected to the external circuit ground so that the regulator and its

capacitors have a single-point ground.

Stability problems have been seen in applications where vias to an internal ground plane were used at the

ground points of the LP38859 device and the input and output capacitors. This was caused by varying ground

potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground

technique for the regulator and its capacitors fixed the problem.

Because high current flows through the traces going into the IN pin and coming from the OUT pin, Kelvin connect

the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors.

10.2 Layout Example

Figure 27. LP38859 Layout Example

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LP38859 Datasheet(PDF) 17 Page - Texas Instruments