SS

IN

BIAS

GND

OUT

10 2F Ceramic

10 2F

Ceramic

1 2F

GND

GND

LP38859-x.x

LP38859

www.ti.com

SNVS337F – JUNE 2006 – REVISED SEPTEMBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP38859 can provide 3-A output current with 240-mV dropout voltage (typical). The bias voltage must be in

The capacitor on the BIAS pin must be at least 1

μF.

8.2 Typical Application

Figure 20. LP38859 Typical Application

8.2.1 Design Requirements

For typical high-accuracy LDO linear regulator applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Bias voltage

3 V to 5.5 V

Input voltage

1.1 V to 5.5 V

Output voltages

0.8 V, 1.2 V

Output current

3 A (maximum)

Bias capacitor

1

μF (minimum)

Input capacitor

10

μF (minimum)

Output capacitor

10 uF (minimum)

8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

To assure regulator stability, input and output capacitors are required as shown in the Figure 20.

8.2.2.1.1

Output Capacitor

A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can

be increased without limit. The output capacitor must be located less than 1 cm from the OUT pin of the device

and returned to the device GND pin with a clean analog ground.

Only high quality ceramic types such as X5R or X7R must be used, as the Z5U and Y5F types do not provide

sufficient capacitance over temperature.

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