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MT4C4M4AX Datasheet(PDF) 18 Page - Micron Technology |
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MT4C4M4AX Datasheet(HTML) 18 Page - Micron Technology |
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18 / 20 page  18 4 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D49_5V.p65 – Rev. 5/00 ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP V V IH IL RAS# tRAS OPEN tCHR tCSR V V IH IL CAS# Q tRP tRAS tRPC tCSR tRPC tCHR tCP V V IH IL tWRP tWRH tWRP tWRH WE# DON’T CARE UNDEFINED NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used. -5 -6 SYMBOL MIN MAX MIN MAX UNITS TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tCHD 15 15 ns tCP 8 10 ns tCSR 5 5 ns tRASS 100 100 µs tRP 30 40 ns tRPC 5 5 ns tRPS 90 105 ns tWRH 8 10 ns tWRP 8 10 ns |
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