TPS62650

TPS62651

SLVS808B

– AUGUST 2009 – REVISED JULY 2011

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THEORY OF OPERATION

Serial Interface Description

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The TPS6265x device works as a slave and supports the following data transfer modes, as defined in the

mode (up to 3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents remain

intact as long as supply voltage remains above 2.1 V (typical).

The data transfer protocol for standard, fast and fast plus modes is exactly the same, therefore, they are referred

to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is

referred to as HS-mode. The TPS6265x device supports 7-bit addressing; 10-bit addressing and general call

address are not supported.

The TPS6265x device has a 7-bit address with two bits factory programmable allowing up to four dc/dc

converters to be connected to the same bus. The 4 MSBs are 1001 and the LSB is 0.

Standard-, Fast- and Fast-Mode Plus Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse, see Figure 51. All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge, see Figure 52, by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link

with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. An

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to

high while the SCL line is high, see Figure 50. This releases the bus and stops the communication link with the

condition, all devices know that the bus is released, and they wait for a start condition followed by a matching

address

Attempting to read data from register addresses not listed in this section results in 00h being read out.

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© 2009–2011, Texas Instruments Incorporated