TPS65279V

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SLVSBW1B – FEBRUARY 2013 – REVISED JANUARY 2014

TERMINAL FUNCTIONS (continued)

NO.

NO.

NAME

DESCRIPTION

(HTSSOP)

(QFN)

BST2

30

29

Add a bootstrap capacitor between BST2 and LX2. The voltage on this

capacitor carries the gate drive voltage for the high-side MOSFET of

Buck 2.

VOUT2

31

30

enabled, output voltage can be programmed from 0.68 V to 1.95 V with

10-mV steps. In current sharing application, connect this pin to the

ground.

FB2

32

31

Feedback sensing pin for the external feedback resistors in Buck 2.

connects to this pin to pre-set the output voltage.

Exposed Thermal Pad

33

37

Exposed thermal pad of the package. Connect to the power ground.

Always solder thermal pad to the board, and have as many vias as

possible on the PCB to enhance power dissipation. There is no electric

signal down bonded to the thermal pad inside the IC package.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

Voltage range at VIN, PVIN1,PVIN2

–0.3 to 20

V

Voltage range at LX1, LX2 (maximum withstand voltage transient < 20 ns)

–4.5 to 20

V

Voltage at BST1, BST2, referenced to LX1, LX2 pin

–0.3 to 7

V

Voltage at V7V, EN1, EN2, VOUT1, VOUT2, MODE

–0.3 to 7

V

Voltage at SS1, SS2, FB1, FB2, COMP1, COMP2

–0.3 to 3

V

Voltage at SDA, SCL, ADDR, EN1, EN2, ROSC

–0.3 to 7

Voltage at AGND, PGND1, PGND2

–0.3 to 0.3

V

Operating virtual junction temperature range

–40 to 150

°C

Storage temperature range

–55 to 150

°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

TPS65279V

THERMAL METRIC

DAP

RHH

UNITS

32 PINS

36 PINS

35

30.8

17.7

18.8

19

6

°C/W

0.5

0.2

18.9

6

1.3

0.7

(1)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(5)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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