TPS65279V datasheet(30/46 Pages) TI

30 / 46 page

TPS65279V

SLVSBW1B – FEBRUARY 2013 – REVISED JANUARY 2014

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Serial Interface Description

I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The TPS65279V device works as a slave and supports the following data transfer modes, as defined in the I2C-

Bus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the

power supply solution, enabling most functions to be programmed to new values depending on the instantaneous

application requirements. Register contents remain intact as long as supply voltage remains above 4.5 V

(typical).

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as

F/S-mode in this document. The TPS65279V device supports 7-bit addressing; 10-bit addressing and general

call address are not supported.

The TPS65279V device has a 7-bit address with the 2 LSB bits set by ADDR pin. Connecting ADDR to ground

set the address 0x60H, connecting to high set the address 0x61H, leaving this pin open set the address 0x62H.

Table 1. I2C Address

Selection

ADDR PIN

I2C ADDRESS

Connect to

0x60H

Ground

Open

0x61H

Connect to High

0x62H

Figure 46. I2C Interface Timing Diagram

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