1

Start By

Master

ACK By

Device

ACK By

Device

Start By

Master

ACK By

Device

ACK By

Master

From

Device

1

9

1

9

1

9

1

9

SDA

SCL

0

0

0

R/

W

P7

P6

P5

P4

P3

P2

P1

P0

SDA

SCL

(Continued)

SDA

SCL

1

0

0

0

0

0

0

(1)

0

0

0

(1)

R/

W

D7

D6

D5

D4

D3

D2

D1

D0

Stop By

Master

NACK By

Master

(2)

From

Device

1

9

D7

D6

D5

D4

D3

D2

D1

D0

Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

Frame 3 Two-Wire Slave Address Byte

Frame 4 MSB

Frame 5 LSB

1

Start By

Master

ACK By

Device

ACK By

Device

ACK By

Device

Stop By

Master

1

9

1

1

D7

D6

D5

D4

D3

D2

D1

D0

9

ACK By

Device

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

0

0

0

0

(1)

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

Frame 4 LSB

Frame 3 MSB

TMP006, TMP006B

SBOS518E – MAY 2011 – REVISED APRIL 2015

www.ti.com

(1) Slave address 1000000 shown. Slave address changes for the TMP006 and TMP006B depend on the ADR1 and ADR0 pin connection.

See Table 4 for more details.

Figure 12. Two-Wire Timing Diagram For Write Word Format

(1) Slave address 1000000 shown.

(2) Master must leave SDA high to terminate a two-byte read operation.

Figure 13. Two-Wire Timing Diagram For Two-Byte Read Format

18

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