AS3630 datasheet(13/72 Pages) AMSCO

13 / 72 page

8A Supercap Flash Driver

AS3630 – 13

tDEBTXMASK

debounce timer

TXMASK/TORCH input in TXMask

mode - see “TXMASK” on page 28

2.1

μs

I²C Mode Timings (page 14 )

fSCLK

SCL Clock

Frequency

0400

kHz

tBUF

Bus Free Time

Between a STOP

and START

Condition

1.3

μs

tHD:STA

Hold Time

(Repeated) START

Condition4

0.6

μs

tLOW

LOW Period of

SCL Clock

1.3

μs

tHIGH

HIGH Period of

SCL Clock

0.6

μs

tSU:STA

Setup Time for a

Repeated START

Condition

0.6

μs

tHD:DAT

Data Hold Time5

00.9

μs

tSU:DAT

Data Setup Time6

100

μs

Rise Time of Both

SDA and SCL

Signals

20 +

0.1CB

300

Fall Time of Both

SDA and SCL

Signals

20 +

0.1CB

300

tSU:STO

Setup Time for

STOP Condition

0.6

μs

Capacitive Load

for Each Bus Line

CB — total capacitance of one bus

line in pF

400

CI/O

I/O Capacitance

(SDA, SCL)

1. In pre-charge the Supercap is always charged close to VVIN; therefore VSUPERCAP_EOC ≥ VVIN is possible

2. In order to reduce the total charging time of the Supercap, it is recommended to keep the Supercap pre-charged at VIN (can be enabled/dis-

able by mode_setting)

3. Due to slope compensation of the current limit, the current limit changes with duty cycle

4. After this period, the first clock pulse is generated.

5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the unde-

fined region of the falling edge of SCL.

6. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then be met. This is automatically

the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it

must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

AS3630 Datasheet(PDF) 13 Page - ams AG

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