AD5672R datasheet(25/34 Pages) AD

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Data Sheet

AD5672R/AD5676R

Rev. B | Page 25 of 34

SERIAL INTERFACE

The AD5672R/AD5676R use a 3-wire serial interface (SYNC,

SCLK, and SDI that is compatible with SPI, QSPI™, and

MICROWIRE interface standards, as well as most DSPs. See

Figure 2 for a timing diagram of a typical write sequence. The

AD5672R/AD5676R contain an SDO pin to allow the user to

daisy-chain multiple devices together (see the Daisy-Chain

Operation section) or for readback.

Input Shift Register

The input shift register of the AD5672R/AD5676R is 24 bits

wide. Data is loaded MSB first (DB23), and the first four bits are

the command bits, C3 to C0 (see Table 10), followed by the 4-

bit DAC address bits, A3 to A0 (see Table 11), and finally, the

bit data-word.

The data-word comprises 12-bit or 16-bit input code, followed by

zero or four don’t care bits for the AD5676R and AD5672R,

respectively (see Figure 60 and Figure 61). These data bits are

transferred to the input register on the 24 falling edges of SCLK

and are updated on the rising edge of SYNC.

Commands execute on individual DAC channels, combined DAC

channels, or on all DACs, depending on the address bits selected.

Table 10. Command Definitions

Command

Description

No operation

Write to Input Register n where n = 1 to 8,

depending on the DAC selected from the

address bits in Table 11 (dependent

on LDAC)

Update DAC Register n with contents of

Input Register n

Write to and update DAC Channel n

Power down/power up the DAC

Hardware LDAC mask register

Software reset (power-on reset)

Internal reference and gain setup register

Set up the DCEN register (daisy-chain

enable)

Set up the readback register (readback

enable)

Update all channels of the input register

simultaneously with the input data

Update all channels of the DAC register

and input register simultaneously with

the input data

Reserved

…

Reserved

Table 11. Address Commands

Channel Address[3:0]

Selected Channel1

DAC 0

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

DAC 7

Any combination of DAC channels can be selected using the address bits.

DB23 (MSB)

D11

D10

COMMAND BITS

ADDRESS BITS

DATA BITS

DB0 (LSB)

Figure 60. AD5672R Input Shift Register Content

DB23 (MSB)

DB0 (LSB)

D11

D10

D15

D14

D13

D12

COMMAND BITS

ADDRESS BITS

DATA BITS

Figure 61. AD5676R Input Shift Register Content

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