AD5672R datasheet(27/34 Pages) AD

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Data Sheet

AD5672R/AD5676R

Rev. B | Page 27 of 34

READBACK OPERATION

Readback mode is invoked through a software executable

readback command. If the SDO output is disabled via the daisy-

chain mode disable bit in the control register, it is automatically

enabled for the duration of the read operation, after which it is

disabled again. Command 1001 is reserved for the readback

function. This command, in association with the address bits

A3 to A0, selects the DAC input register to read (see Table 10

and Table 11). Note that, during readback, only one input

sequence are don’t care bits. During the next SPI write, the data

appearing on the SDO output contains the data from the

previously addressed register.

For example, to read back the DAC register for Channel 0,

implement the following sequence:

1. Write 0x900000 to the AD5672R/AD5676R input register.

This configures the device for read mode with the DAC

to DB0, are don’t care bits.

2. Follow this with a second write, a no operation (NOP)

condition, 0x000000. During this write, the data from the

contain undefined data, and the last 16 bits contain the

DB19 to DB4 DAC register contents.

When SYNC is high, the SDO pin is driven by a weak latch that

holds the last data bit. The SDO pin can be overdriven by the

SDO pin of another device, thus allowing multiple devices to be

read using the same SPI interface.

POWER-DOWN OPERATION

The AD5672R/AD5676R contain two separate power-down

modes. Command 0100 is designated for the power-down

function (see Table 10). These power-down modes are software

programmable by setting 16 bits, Bit DB15 to Bit DB0, in the

input shift register. There are two bits associated with each DAC

channel. Table 13 shows how the state of the two bits corresponds

to the mode of operation of the device.

Any or all DACs (DAC A to DAC D) power down to the

selected mode by setting the corresponding bits. See Table 14

for the contents of the input shift register during the power-

down/power-up operation.

Table 13. Modes of Operation

Operating Mode

PD1

PD0

Normal Operation

Power-Down Modes

1 kΩ to GND

Tristate

When both Bit PD1 and Bit PD0 in the input shift register are set to

0, the device works normally with a typical power consumption of

1 mA at 5 V. However, for the two power-down modes, the

supply current typically falls to 1 µA. In addition to this fall, the

output stage switches internally from the amplifier output to a

resistor network of known values. This has the advantage that the

output impedance of the devices is known while the devices are

in power-down mode. There are two different power-down

options. The output is either connected internally to GND

through a 1 kΩ resistor or it is left open-circuited (tristate).

Figure 63 shows the output stage.

RESISTOR

NETWORK

VOUT

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 63. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry shut down when power-down mode is

activated. However, the contents of the DAC register are unaffected

when in power-down. The DAC register updates while the device

is in power-down mode. The time required to exit power-down is

typically 2.5 µs for VDD = 5 V.

To reduce the current consumption further, power off the on-chip

reference. See the Internal Reference Setup section.

Table 14. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation

[DB23:DB20]

DB19

[DB18:DB16]

DAC 7

DAC 6

DAC 5

DAC 4

DAC 3

DAC 2

DAC 1

DAC 0

[DB15: B14]

[DB13: B12]

[DB11: B10]

[DB9:DB8]

[DB7:DB6]

[DB5:DB4]

[DB3:DB2]

[DB1:DB0]

0100

XXX1

[PD1:PD0]

X means don’t care

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