AD7402

Data Sheet

Rev. A | Page 16 of 20

The recommended circuit configuration for driving the

differential inputs to achieve best performance is shown in

Figure 28. An RC low-pass filter is placed on both the analog

input pins. Recommended values for the resistors and capacitors

are 10 Ω and 220 pF, respectively. If possible, equalize the

source impedance on each analog input to minimize offset.

Figure 28. RC Low-Pass Filter Input Network

The input filter configuration for the AD7402 is not limited to

the low-pass structure shown in Figure 28. The differential RC

filter configuration shown in Figure 29 also achieves excellent

performance. Recommended values for the resistors and

capacitor are 22 Ω and 47 pF, respectively.

Figure 29. Differential RC Filter Network

Figure 30 compares the typical performance for the input filter

structures outlined in Figure 28 and Figure 29 for different

resistor and capacitor values.

Figure 30. SNR vs. Decimation Rate for Different Filter Structures for Different

Resistor and Capacitor Values

DIGITAL FILTER

The output of the AD7402 is a continuous digital bit stream. To

reconstruct the original input signal information, this output bit

stream needs to be digitally filtered and decimated. A sinc filter

is recommended due to its simplicity. A sinc3 filter is

recommended because it is one order higher than that of the

AD7402 modulator, which is a second-order modulator. The type

of filter selected, the decimation rate, and the modulator clock used

determines the overall system resolution and throughput rate. The

higher the decimation rate, the greater the system accuracy, as

illustrated in Figure 31. However, there is a trade-off between

accuracy and throughput rate and, therefore, higher decimation

rates result in lower throughput solutions.

Figure 31. SNR vs. Decimation Rate for Different Sincx Filter Orders

A sinc3 filter is recommended for use with the AD7402. This

filter can be implemented on a field programmable gate array

(FPGA) or a digital signal processor (DSP).

Equation 1 describes the transfer function of a sinc filter.

(

)

(

)

N

DR

Z

Z

DR

z

H













−

−

=

−

−

1

1

1

1

)

(

(1)

where DR is the decimation rate and N is the sinc filter order.

The throughput rate of the sinc filter is determined by the

modulator clock and the decimation rate selected.

DR

MCLK

Throughput =

(2)

where MCLK is the modulator clock frequency

As the decimation rate increases, the data output size from the

sinc filter increases. The output data size is expressed in

Equation 3. The 16 most significant bits are used to return a

16-bit result.

(3)

from the filter transfer function, Equation 1, and is 0.262 times

the throughput rate. The filter characteristics for a third-order

sinc filter are summarized in Table 11.

Table 11. Sinc3 Filter Characteristics for 10 MHz

Decimation

Ratio (DR)

Throughput

Rate (kHz)

Output Data

Size (Bits)

Filter Response

(kHz)

32

312.5

15

81.8

64

156.2

18

40.9

128

78.1

21

20.4

256

39.1

24

10.2

512

19.55

27

5.1

R

VIN–

R

VIN+

C

C

AD7402

R

R

C

AD7402

DECIMATION RATE

45

50

55

60

65

70

75

80

85

90

95

10

100

10Ω, 220pF

DIFFERENTIAL 22Ω, 47pF

DIFFERENTIAL 22Ω, 10nF

DECIMATION RATE

0

10

20

30

40

50

60

70

80

90

100

10

100

SINC1

SINC2

SINC3

SINC4