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Data Sheet

AD7402

Rev. A | Page 3 of 20

SPECIFICATIONS

VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +105°C, tested with sinc3 filter, 256

decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

Bits

Filter output truncated to 16 bits

Integral Nonlinearity (INL)1

±1

±5

LSB

Differential Nonlinearity (DNL)1

±0.99

LSB

Guaranteed no missed codes to 16 bits

Offset Error1

±0.2

±0.75

Offset Drift vs. Temperature

1.7

µV/°C

Offset Drift vs. VDD1

µV/V

Gain Error1

0.2

±0.5

% FSR

Gain Error Drift vs. Temperature

ppm/°C

µV/°C

Gain Error Drift vs. VDD1

0.2

mV/V

ANALOG INPUT

Input Voltage Range

−320

+320

Input Common-Mode Voltage Range

−200 to +300

Dynamic Input Current

±19

±28

µA

VIN+ = ±250 mV, VIN− = 0 V

0.05

µA

VIN+ = 0 V, VIN− = 0 V

Input Capacitance

DYNAMIC SPECIFICATIONS

VIN+ = 35 Hz

Signal-to-(Noise + Distortion) Ratio (SINAD)1

Signal-to-Noise Ratio (SNR)1

Total Harmonic Distortion (THD)1

−84

Peak Harmonic or Spurious Noise (SFDR)1

−84

Effective Number of Bits (ENOB)1

13.5

Bits

Noise Free Code Resolution1

Bits

ISOLATION TRANSIENT IMMUNITY1

kV/µs

LOGIC OUTPUTS

Output High Voltage, VOH

VDD2 − 0.1

IO = −200 µA

Output Low Voltage, VOL

0.4

IO = +200 µA

POWER REQUIREMENTS

VDD1

4.5

5.5

VDD2

5.5

IDD1

VDD1 = 5.5 V

IDD2

VDD2 = 5.5 V

4.5

5.5

VDD2 = 3.3 V

POWER DISSIPATION

209

VDD1 = VDD2 = 5.5 V

See the Terminology section.

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