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Data Sheet

AD7402

Rev. A | Page 17 of 20

The following Verilog code provides an example of a sinc3 filter

implementation on a Xilinx® Spartan®-6 FPGA. Note that the

data is read on the negative clock edge. It is recommended to

read in the data on the negative clock edge. The code is

configurable to accommodate decimation rates from 32 to 4096.

module dec256sinc24b

(

input mclk1,

/* used to clk filter */

input reset,

/* used to reset filter */

input mdata1, /* input data to be filtered

output reg [15:0] DATA, /* filtered output

output reg data_en,

input [15:0] dec_rate

);

/* Data is read on negative clk edge */

reg [36:0] ip_data1;

reg [36:0] acc1;

reg [36:0] acc2;

reg [36:0] acc3;

reg [36:0] acc3_d2;

reg [36:0] diff1;

reg [36:0] diff2;

reg [36:0] diff3;

reg [36:0] diff1_d;

reg [36:0] diff2_d;

reg [15:0] word_count;

reg word_clk;

reg enable;

/*Perform the Sinc action*/

always @ (mdata1)

if(mdata1==0)

ip_data1 <= 37'd0;

/* change 0 to a -1 for twos

complement */

else

ip_data1 <= 37'd1;

/*Accumulator (Integrator)

Perform the accumulation (IIR) at the speed

of the modulator.

Z = one sample delay MCLKOUT = modulators

conversion bit rate */

Figure 32. Accumulator

always @ (negedge mclk1, posedge reset)

begin

if (reset)

begin

/* initialize acc registers on reset

acc1 <= 37'd0;

acc2 <= 37'd0;

acc3 <= 37'd0;

end

else

begin

/*perform accumulation process */

acc1 <= acc1 + ip_data1;

acc2 <= acc2 + acc1;

acc3 <= acc3 + acc2;

end

/*decimation stage (MCLKOUT/WORD_CLK) */

always @ (negedge mclk1, posedge reset)

begin

if (reset)

word_count <= 16'd0;

else

begin

if ( word_count == dec_rate -

1 )

word_count <= 16'd0;

else

word_count <= word_count

+ 16'b1;

end

always @ ( negedge mclk1, posedge reset )

begin

if ( reset )

word_clk <= 1'b0;

else

begin

if ( word_count == dec_rate/2 -

1 )

word_clk <= 1'b1;

else if ( word_count ==

dec_rate - 1 )

word_clk <= 1'b0;

end

/*Differentiator (including decimation

stage)

Perform the differentiation stage (FIR) at a

lower speed.

Z = one sample delay WORD_CLK = output word

rate */

Figure 33. Differentiator

always @ (negedge word_clk, posedge reset)

begin

if(reset)

begin

acc3_d2 <= 37'd0;

diff1_d <= 37'd0;

diff2_d <= 37'd0;

MCLKIN

IP_DATA1

ACC1+

ACC2+

ACC3+

WORD_CLK

ACC3

DIFF1

DIFF3

–

DIFF2

Z–1

–

Z–1

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