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AD7402

Data Sheet

Rev. A | Page 18 of 20

diff1 <= 37'd0;

diff2 <= 37'd0;

diff3 <= 37'd0;

end

else

begin

diff1 <= acc3 - acc3_d2;

diff2 <= diff1 - diff1_d;

diff3 <= diff2 - diff2_d;

acc3_d2 <= acc3;

diff1_d <= diff1;

diff2_d <= diff2;

end

/* Clock the Sinc output into an output

WORD_CLK = output word rate */

Figure 34. Clocking Sinc3 Output into an Output Register

always @ (negedge word_clk )

begin

case ( dec_rate )

16'd32:begin

DATA <= (diff3[15:0] ==

16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};

end

16'd64:begin

DATA <= (diff3[18:2] ==

17'h10000) ? 16'hFFFF : diff3[17:2];

end

16'd128:begin

DATA <= (diff3[21:5] ==

17'h10000) ? 16'hFFFF : diff3[20:5];

end

16'd256:begin

DATA <= (diff3[24:8] ==

17'h10000) ? 16'hFFFF : diff3[23:8];

end

16'd512:begin

DATA <= (diff3[27:11] ==

17'h10000) ? 16'hFFFF : diff3[26:11];

end

16'd1024:begin

DATA <= (diff3[30:14] ==

17'h10000) ? 16'hFFFF : diff3[29:14];

end

16'd2048:begin

DATA <= (diff3[33:17] ==

17'h10000) ? 16'hFFFF : diff3[32:17];

end

16'd4096:begin

DATA <= (diff3[36:20] ==

17'h10000) ? 16'hFFFF : diff3[35:20];

end

default:begin

DATA <= (diff3[24:8] ==

17'h10000) ? 16'hFFFF : diff3[23:8];

end

endcase

end

/* Synchronize Data Output*/

always@ (negedge mclk1, posedge reset )

begin

if ( reset )

begin

data_en <= 1'b0;

enable <= 1'b1;

end

else

begin

if ( (word_count == dec_rate/2

- 1) && enable )

begin

data_en <= 1'b1;

enable <= 1'b0;

end

else if ( (word_count ==

dec_rate - 1)

&& ~enable )

begin

data_en <= 1'b0;

enable <= 1'b1;

end

else

data_en <= 1'b0;

end

endmodule

WORD_CLK

DATA

DIFF3

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