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DLPA2000 Datasheet(PDF) 3 Page - Texas Instruments |
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DLPA2000 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 58 page ![]() D C B A 4 3 2 1 5 E F 6 G 7 H SW5 AOUT1 RLIM BOUT1 PGND CM VCORE SW4 LED_ SEL1 RLIM_ K LS_IN LS_ OUT VLED SENS1 SENS2 VLED PROJ_ ON DGND V2V5 L2 VSPI CMP_ OUT L2 PWM_ IN AGND VINA PGNDL SPI_ CLK SPI_ CSZ PGNDL SPI_ DIN SPI_ DOUT VOFS L1 RESET Z INTZ L1 CNTR_ VRST REF_ VRST VBIAS VINL AGND1 VINR VINL SWN PGNDR SWP SW6 V6V AOUT2 RLIM BOUT2 VINC SWC LED_ SEL0 VINM RBOT_ K DLPA2000 www.ti.com DLPS043A – JUNE 2014 – REVISED AUGUST 2015 5 Pin Configuration and Functions YFF PACKAGE 56-PIN DSGBA BOTTOM VIEW Pin Functions PIN I/O DESCRIPTION NAME NUMBER A1 VINL I Power supply input for VLED BUCK-BOOST power stage. Connect to system power. A2 AGND1 A3 GND Analog ground. Connect to ground plane. VINR A4 I Power supply input for DMD switch mode power supply (SMPS). Connect to system power. SWN A5 I Connection for the DMD SMPS-inductor (high-side switch). PGNDR A6 GND Power ground for DMD SMPS. Connect to ground plane. SWP A7 O Connection for the DMD SMPS-inductor (low-side switch). B1 L1 O Connection for VLED BUCK-BOOST inductor. B2 RESETZ B3 O Reset output to the DLP system (active low). Pin is held low to reset DLP system. INTZ B4 O Interrupt output signal (open drain). Connect to pullup resistor or short to ground. CNTR_VRST B5 O Connection to VRST for fast discharge function REF_VRST B6 I Reference pin for the VRST regulator. Connect to VRST rail through 100-k Ω resistor. VBIAS B7 O VBIAS output rail. Connect to ceramic capacitor. C1 PGNDL GND Power ground for VLED BUCK-BOOST. Connect to ground plane. C2 SPI_CLK C3 I Clock input for SPI interface SPI_CSZ C4 I SPI chip select (active low) SPI_DIN C5 I SPI data input Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DLPA2000 |
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