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tCSCR

tCDS

tCDH

tCFDO

tCFCS

tCSZ

HiZ

SPI_CSZ

(SS)

SPI_CLK

(SCLK)

SPI_DIN

(MOSI)

SPI_DOUT

(MISO)

tiS

tiH

tCLKL

tCLKH

DLPA2000

DLPS043A – JUNE 2014 – REVISED AUGUST 2015

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6.8 Data Transmission Timing Requirements

VBAT = 3.6 ± 5%, TA = 25 ºC, CL = 10 pF (unless otherwise noted)

MIN

NOM

MAX

UNIT

ƒCLK

Serial clock frequency

MHz

tCLKL

Pulse width low, SPI_CLK, 50% level

tCLKH

Pulse width high, SPI_CLK, 50% level

Transition time, 20% to 80% level, all signals

0.2

tCSCR

SPI_CSZ falling to SPI_CLK rising, 50% level

tCFCS

SPI_CLK falling to SPI_CSZ rising, 50% level

tCDS

SPI_DIN data setup time, 50% level

tCDH

SPI_DIN data hold time, 50% level

tiS

SPI_DOUT data setup time(1)), 50% level

tiH

SPI_DOUT data hold time (1), 50% level

tCFDO

SPI_CLK falling to SPI_DOUT data valid, 50% level

tCSZ

SPI_CSZ rising to SPI_DOUT HiZ

(1)

The DPPxxxx processors send and receive data on the falling edge of the clock.

Figure 2. SPI Timing Diagram

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