LAN8810 datasheet(25/83 Pages) MICROCHIP

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DS00001870B-page 25

LAN8810/LAN8810I

Section 3.8.1.2.3 describes how the MOD field controls other configuration bits in the device. When a soft reset is issued

via the PHY Soft Reset (RESET) bit of the Basic Control Register, configuration is controlled by the register bit values

and the CONFIG[3:0] pins have no affect. Likewise, changing the MOD field of the Extended Mode Control/Status Reg-

ister bits does not change the configuration of the device in this case.

3.8.1.2.3

Configuration Bits Impacted by the Mode of Operation

Immediately after a reset, the MOD field of the Extended Mode Control/Status Register will be set dependent on the

configuration pin values of the CONFIG3 and CONFIG2 pins, as described in Section 3.8.1.2.2. Table 3-9 details how

the MOD field effects other device configuration register bits.

Note:

Table 3-8 utilizes register index and bit number referencing in lieu of individual names.

TABLE 3-9:

CONFIGURING THE MODE OF OPERATION

Mode Definitions

CONFIG3

CONFIG2

Reg 19

[15:11]

10BASE-T Half Duplex. Auto-negotiation disabled.

CPV(2)

CPV(0)

00000

10BASE-T Full Duplex. Auto-negotiation disabled.

CPV(2)

CPV(1)

00001

100BASE-TX Half Duplex. Auto-negotiation disabled.

CRS is active during Transmit & Receive.

CPV(2)

00010

100BASE-TX Full Duplex. Auto-negotiation disabled.

CRS is active during Receive.

CPV(2)

CPV(3)

00011

All mode capable (10/100/1000). Auto-negotiation enabled.

Auto master/slave resolution single port.

CPV(3)

CPV(0)

00111

10BASE-T/100BASE-TX capable. Auto-negotiation enabled.

CPV(3)

CPV(1)

00100

All mode capable (10/100/1000). Auto-negotiation enabled.

Manual master/slave resolution slave port.

CPV(3)

CPV(2)

01001

All mode capable (10/100/1000). Auto-negotiation enabled.

Manual master/slave resolution master port.

CPV(3)

01010

Note:

Table 3-9 utilizes register index and bit number referencing in lieu of individual names

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