LAN8810 datasheet(28/83 Pages) MICROCHIP

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LAN8810/LAN8810I

DS00001870B-page 28

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3.9.2

VARIABLE VOLTAGE I/O

The device’s digital I/O pins are variable voltage, allowing them to take advantage of low power savings from shrinking

technologies. These pins can operate at +2.5V or 3.3V. The applied I/O voltage must maintain its value within the toler-

ances specified in Section 5.0, "Operational Characteristics," on page 60. Varying the voltage up or down after the trans-

ceiver has completely powered-on can cause errors in the transceiver operation. Refer to Section 5.0, "Operational

Characteristics," on page 60 for additional information.

3.9.3

ISOLATE MODE

The device data paths may be electrically isolated from the GMII interface by setting the Isolate bit of the Basic Control

respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same GMII interface without contention. By

default, the transceiver is not isolated (on power-up, Isolate=0).

3.9.4

CARRIER SENSE

The carrier sense signal is output on CRS. Carrier sense operation is defined in the IEEE 802.3u standard. The PHY

asserts carrier sense based only on receive activity whenever the PHY is either in repeater mode or full-duplex mode.

Otherwise, the PHY asserts carrier sense based on either transmit or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier

sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 con-

secutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is

asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after

the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE

followed by some non-IDLE symbol.

3.9.5

COLLISION DETECT

A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate

that a collision has been detected. COL remains active for the duration of the collision. COL is changed asynchronously

to both RXCLK and TXCLK. A collision can only occur in half-duplex mode. The COL output becomes inactive during

full duplex mode.

COL may be tested by setting the Collision Test bit of the Basic Control Register. This enables the collision test. COL

will be asserted within 512 bit times of TXEN rising and will be de-asserted within 4 bit times of TXEN falling.

In 10BASE-T mode, COL pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de-assertion

of TXEN). This serves as the Signal Quality Error (SQE) signal and indicates that the transmission was successful.

TABLE 3-13:

LED MODE 3 OPERATION - LED_MODE[1:0]=11B

LED

STATUS

DESCRIPTION

1000_LED

1000BASE-T link

Blinking

Transmit/receive activity

100_LED

100BASE-T link

Blinking

Transmit/receive activity

10_LED

10BASE-T link

Blinking

Transmit/receive activity

ACT_LED

Link operates at full duplex

Off

Link operates at half duplex

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