LAN8810 datasheet(48/83 Pages) MICROCHIP

48 / 83 page

LAN8810/LAN8810I

DS00001870B-page 47

 2009-2015 Microchip Technology Inc.

Note 4-6

The default is determined by the CONFIG[1:0] pins as described in Section 3.8.1.2.1, "Configuring

the SMI Address (CONFIG[1:0])," on page 25.

4.2.16

EXTENDED MODE CONTROL/STATUS REGISTER

4:0

PHYADD[4:0]

The PHY Address is used for the SMI address and for the initialization of the

Cipher (Scrambler) key.

R/W

NASR

Note 4-6

Index (In Decimal): 19

Size:

16 bits

Bits

Description

Type

Default

15:11

MOD

Configures mode of operation. Refer to Section 3.8.1.2.2, "Configuring the

Mode of Operation (CONFIG[3:2])," on page 26 for details.

Note:

The MOD bits should not be modified and must be preserved

when writing to this register.

R/W

NASR

Note 4-7

10:9

Transmitter FIFO Depth

00 = 4 bytes

01 = 5 bytes

10 = 6 bytes

11 = 7 bytes

R/W

00b

8:6

RESERVED

These bits must be written as 000b.

5:4

LED_MODE[1:0]

00 = Reserved

01 = LED mode 1

10 = LED mode 2

11 = LED mode 3

Refer to Section 3.9.1, "LEDs," on page 26 for additional information.

R/W

11b

RESERVED

This bit must be written as 1b

R/W

MDI/MDI-X 0:1

Selects between MDI and MDI-X for channel 0 and channel 1 only if the Auto

MDIX Disable bit of the 10/100 Mode Control/Status Register is 1.

0 = MDI

1 = MDI-X

MDI/MDI-X 2:3

Selects between MDI and MDI-X for channel 2 and channel 3 only if the Auto

MDIX Disable bit of the 10/100 Mode Control/Status Register is 1.

0 = MDI

1 = MDI-X

CONDITIONAL PARALLEL DETECT

0 = Parallel detect. (Auto Negotiation Advertisement Register is ignored.)

1 = Conditional Parallel Detect only at the speed advertised in the Auto

Negotiation Advertisement Register.

10BASE-T half duplex (10BASE-T bit =1)

100BASE-TX half duplex (100BASE-TX bit =1)

Bits

Description

Type

Default

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