LAN8810 datasheet(30/83 Pages) MICROCHIP

30 / 83 page

LAN8810/LAN8810I

DS00001870B-page 30

 2009-2015 Microchip Technology Inc.

• If auto-negotiation is not enabled, the device transmits NLPs in 10BASE-T mode, and MLT-3s in 100BASE-TX

mode.

3.9.7

SPEED OPTIMIZER

The Speed Optimize function is designed to resolve the issue of using auto-negotiation to establish a link on impaired

cable plants.

Examples of impaired cable plants for 1000BASE-T (Gigabit) connections include:

• Channel 2 twisted pair cable plant is broken

• Channel 3 twisted pair cable plant is broken

• Channel 2 and 3 twisted pair cable plants are broken

• Cable plant is too long

Examples of impaired cable plants for 100BASE-TX connections include:

• Cable plant is too long

• Using wrong cable plant (such as CAT-3)

The Speed Optimize function requires the MAC to support 1000/100/10 Mbps speeds, 1000/100 Mbps speeds, 1000/

10 Mbps or 100/10 Mbps speeds.

If a link fails to establish after the link partners go through auto-negotiation several times at the HCD (Highest Common

Denominator), the device advertises the next highest-allowable speed (as set in the Auto Negotiation Advertisement

When 1000BASE-T is advertised, the Speed Optimize function can change its advertised speed from 1000BASE-T to

100BASE-TX and from 100BASE-TX to 10BASE-T. When 100BASE-TX is advertised, the Speed Optimize function can

change its advertised speed from 100BASE-TX to 10BASE-T. If a previous link has used the Speed Optimize function

to establish a link, when the link goes down, the device begins advertising with all capable speeds.

The Speed Optimize function resets itself to advertise HCD/all speed capabilities after any of the following occurrences:

• Hardware reset

• Software reset

• While link partners exchange link pulses through the Speed Optimize process, the device does not receive link

pulses for a period of few seconds

• After an established link goes down

The Speed Optimize function is enabled via Speed Optimize Enable bit in the 10/100 Mode Control/Status Register.

When a link (with a speed slower than HCD) is being established through the Speed Optimize process, it is reported via

the Speed Optimize Status bit in the User Status 2 Register.

3.9.8

LOOPBACK OPERATION

The local loopback mode is enabled by setting the Loopback bit of the Basic Control Register. In this mode, the scram-

bled transmit data (output of the scrambler) is looped into the receive logic (input of the descrambler). This mode is use-

ful as a board diagnostic and serves as a quick functional verification of the device. The COL signal will be inactive in

this mode, unless the Collision Test bit of the Basic Control Register is set.

3.9.9

IEEE 1149.1 (JTAG) BOUNDARY SCAN

The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four

pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and an instruction register. The JTAG

pins are described in Table 2-5, "JTAG Pins". The JTAG interface conforms to the IEEE Standard 1149.1 - 1990 Stan-

dard Test Access Port (TAP) and Boundary-Scan Architecture

All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into

the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.

The JTAG logic is reset via a hardware reset or when the TMS and TDI pins are high for five TCK periods.

Note:

During transmission in local loopback mode, nothing is transmitted to the line and the transmitters are pow-

ered down.

LAN8810 Datasheet(PDF) 30 Page - Microchip Technology

LAN8810 Datasheet(HTML) 30 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL