TUSB3210PM datasheet(39/50 Pages) TI1

39 / 50 page

CLK

RESET

VCC

90%

3.3 V

1.2 V

0 V

>60

µs

100

µs < RESET TIME

1.8 V

RESET TIME < 30 ms

TUSB3210

www.ti.com

SLLS466G – FEBRUARY 2001 – REVISED DECEMBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Reset Timing

There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100

μs. At

power up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the reset

signal exceeds 1.2 V. The second requirement is that the clock must be valid during the last 60

μs of the reset

window. The third requirement is that, according to the USB specification, the device must be ready to respond

to the host within 100 ms. This means that within the 100-ms window, the device must come out of reset, load

any pertinent data from the I2C EEPROM device, and transfer execution to the application firmware if any is

present. Because the latter two events can require significant time, the amount of that can change from system

to system, TI recommends having the device come out of reset within 30 ms, leaving 70 ms for the other events

to complete. This means the reset signal should rise to 1.8 V within 30 ms.

These requirements are depicted in Figure 7. Notice that when using a 12-MHz crystal or the 48-MHz oscillator,

the clock signal may take several milliseconds to ramp up and become valid after power up. Therefore, the reset

window may need to be elongated up to 10 ms or more to ensure that there is a 60-µs overlap with a valid clock.

Figure 7. Reset Timing

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TUSB3210PM Datasheet(PDF) 39 Page - Texas Instruments