TUSB3210PM datasheet(13/50 Pages) TI1

13 / 50 page

TUSB3210

www.ti.com

SLLS466G – FEBRUARY 2001 – REVISED DECEMBER 2015

7.5.2.5 WDCSR: Watchdog Timer, Control, and Status Register

A watchdog timer (WDT) with 1-ms clock is provided. The watchdog timer works only when a USB start-of-frame

has been detected by the TUSB3210. If this register is not accessed for a period of 32 ms, the WDT counter

resets the MCU (see Figure 3, Reset Diagram). When the IDL bit in PCON is set, the WDT is suspended until an

interrupt is detected. At this point, the IDL bit is cleared and the WDT resumes operation. The WDE bit of this

WDE

WDR

RSV

WDT

R/W

R/O

W/O

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

BIT

NAME

RESET

FUNCTION

The MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If the MCU does not write a 1

WDT

in a period of 31 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (WDT is a 5-bit

counter using a 1-ms CLK.) This bit is read as 0.

5–1

RSV

Reserved = 0

Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog timer

reset.

WDR

WDR = 0

A power-up or USB reset occurred.

A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has no

WDR = 1

effect.

Watchdog timer enable.

WDE

WDE = 0

Disabled

WDE = 1

Enabled

7.5.2.6 PCON: Power Control Register (at SFR 87h)

SMOD

RSV

GF1

GF0

RSV

IDL

R/W

R/O

R/W

R/O

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

BIT

NAME

RESET

FUNCTION

MCU idle mode bit. This bit can be set by the MCU and is cleared only by the INT1 interrupt.

The MCU is not in idle mode. This bit is cleared by the INT1 interrupt logic when INT1 is

IDL = 0

asserted for at least 400

μs.

IDL

The MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and

the WDT is suspended. When in suspend mode, only INT1 can be used to exit from idle

IDL = 1

state and generate an interrupt. INT1 must be asserted for at least 400

μs for the

interrupt to be recognized.

RSV

Reserved

3–2

GF[1:0]

General-purpose bits. The MCU can write and read them.

6–4

RSV

Reserved

Double baud-rate control bit. For more information, see the UART serial interface in the M8052 core

SMOD

specification.

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