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L9662 Datasheet(PDF) 71 Page - STMicroelectronics

Part # L9662
Description  Octal squib driver and quad Manchester/PSI5 encoded sensor
PDF  80 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9662 Datasheet(HTML) 71 Page - STMicroelectronics

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L9662
Functional description
79
Note:
With CHxSF2:CHxSF0 = '000', '001, or '101'
When transferring data if the CRC check is disabled on the ASIC then there is no parity bit
and the CRC bits will be present along with the data bits on the MISO line.
The following describes the bit usage for the CCR command
Bits [D11].
Used to enable/disable checksum calculations in MS satellite
mode (D11 is ignored in PSI5).
0
1
0
odd
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
1
odd
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 SV2 SV1 SV0 CRC2 CRC1 CRC0
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0 SV2 SV1 SV0 CRC2 CRC1 CRC0
0
1
1
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 CRC2 CRC1 CRC0
0
0
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0 CRC2 CRC1 CRC0
0
0
0
0
MISO Data Response in MS Mode: Generic Protocol
0
0
0
odd
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 SV2 SV1 SV0
0
0
0
0
1
odd
D7
D6
D5
D4
D3
D2
D1
D0 SV2 SV1 SV0
0
0
0
0
0
1
0
odd
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
1
odd
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
P
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 SV2 SV1 SV0
0
0
1
0
1
P
D7
D6
D5
D4
D3
D2
D1
D0 SV2 SV1 SV0
0
0
0
0
1
1
0
P
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
1
1
P
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
MISO Data Response in PSI5 Mode: Parity Protocol
X
0
0
odd D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
X
0
1
odd D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
X
1
0
odd
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
X
1
1
odd
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
MISO Data Response in Raw Data Mode
0
X
X
odd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
MISO Data Response in Hall Effect Mode
0
X
X
odd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 40. MISO responses with D14=0 (Data register selection) (continued)
MOSI Bit Setting
MISO Bit Definition
D11 D10 D09 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00



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