L9662 datasheet(22/80 Pages) STMICROELECTRONICS

22 / 80 page

Electrical specifications

L9662

22/80

DocID028325 Rev 1

tFlt _BATT

Output fault filter for short

to battery

V(ICHX)-VSATS>50mV

μs

tFlt _GND

Output fault filter for short

to ground

I_sensor>I_lim

300

360

μs

Receive Mode

VICHx

Output voltage on pin

ICHx (x = 1…4)

IICHx= [0…50mA];

 VSATS  14V

VSAT-1

VSAT

SYNC Mode and High Voltage mode

VICHx_HV

Output voltage during

High Voltage Mode and

SYNC Mode High time

 VSATS  14V (VSATS+6V) 

VSYNC

 25V IICHx = 50mA

VICHx

VREG_DO

Regulator Drop Out

voltage

IICHx = 50mA

2.5

tSYNCDLY

Delay time from rising

edge of INITSYNC pin to

sync pulse voltage active

Measured from INITSYNC pin

rising edge to 5% of VHV

All Channels

2.7

6.6

μs

tSYNC_high1 SYNC pulse high time

-7%

+ 7%

μs

tSYNC_dlyhigh1

Total delay time from

INITSYNC to sync pulse

falling edge

MCR D9:D8=”00”

Measured from INITSYNC pin

rising edge to 90% of sync

pulse falling edge (V ICHx_HV -

V ICHx idle)

All Channels using default slew

rate

20.3

μs

tSYNC_high2 SYNC pulse high time

-7%

+ 7%

μs

tSYNC_high3

SYNC pulse high time

data “0” pulse width (High

voltage mode)

-7%

+ 7%

μs

tSYNC_high4

SYNC pulse high time

data “1” pulse width (High

voltage mode)

-7%

+ 7%

μs

tRECV_disable Receiver disable time

MCR bit D2=0

-7%

+ 7%

μs

MCR bit D2=1

-7%

tSYNC_hi

ghx

typ +

20μs

+ 7%

μs

triseslewrate

High Voltage rise slew rate

for ICHx

MCR bit D3=0

0.9

V/μs

MCR bit D3=1

0.43

1.5

tfallslewrate

High Voltage fall slew rate

for ICHx

MCR bit D3=0

0.9

V/μs

MCR bit D3=1

0.43

1.5

Table 8. Satellite interface - DC electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

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