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L9662 Datasheet(PDF) 38 Page - STMicroelectronics |
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L9662 Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 80 page ![]() Functional description L9662 38/80 DocID028325 Rev 1 High side safing diagnostics When the command is received the ASIC will activate IHSS on the selected VRESx. The diagnostics will measure the difference between VSDIAG and VRESx. The internal comparator will detect open, short or normal condition based on the differential voltage between VSDIAG and VRESx. The results shall be reported in the next SPI message using bits HSS1 and HSS0 as indicated in the following table. Once the command is issued the voltages shall be captured on the next falling edge of CS_D. Voltage measurement diagnostics (VRESx) When the command is received the ASIC will activate a comparator for the selected channel. A 2 bit indication of the state of the VRESx pins shall be reported as indicated below. The results shall be reported in the next SPI message. Once the command is issued the voltages shall be captured on the next falling edge of CS_D. Loss of ground When any of the power grounds (GND0 – 7) are lost, no deployment can occur on the respective deployment channels because the low side driver will be inactive. The high side driver for the respective channel can still be activated. A loss of ground condition on one or several channels will not affect the operation of the remaining channels. When a loss of ground condition occurs, the source of the low side MOS will be floating. In this case, no current will flow through the low side driver. This condition will be detected as a fault by a low side MOS diagnostic. No additional faults will be reported from any other diagnostic due to this condition. Table 13. High side safing diagnostics Condition Diagnostic Mode HSS Selection HSS1 HSS0 (VSDIAG-VRESx) < VHSSSHORT_th 0 0 VHSSSHORT_th < (VSDIAG-VRESx) < VHSSOPEN_th 0 1 VHSSOPEN_th < (VSDIAG-VRESx) 1 1 Table 14. Voltage measurement diagnostics Condition Diagnostic mode 3 VRESx selection VR1 VR0 VRESx < VVRESXLO_th 0 0 VVRESXLO_th < VRESx < VVRESXHI_th 0 1 VVRESXHI_th < VRESx 1 1 |
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