L9662 datasheet(28/80 Pages) STMICROELECTRONICS

28 / 80 page

Functional description

L9662

28/80

DocID028325 Rev 1

3.3

Serial peripheral interface (SPI)

The device contains 2 serial peripheral interfaces for control of the satellite and squib

functions. The 2 SPI interfaces are completely independent from each other and can be

accessed simultaneously. The following table shows the distribution of features that are

accessed/controlled for each of the SPIs

The software reset accessed over SPI1 will not only reset squib functions but all the satellite

functions. The device has a counter to verify the number of clocks in SCLK and SCLK_S.

L9662 computes SPI error length flag by counting the number of SCLK/SCLK_S rising

edges occurring when CS_D/CS_S is active. If the number of clocks in SCLK is not equal to

16 clocks while CS_D is asserted, it ignores the SPI message and sends a SPI fault

response. If the number of clocks in SCLK_S is not equal to 80 clocks while CS_S is

asserted it ignores the entire SPI message and a fault will be reported in the SR frame. The

MISO output on SPI1 shall hold the 16th bit’s state for SCLK rising edges greater than 16

when CS_D is active, similarly the MISO output on SPI2 shall hold the 80th bit’s state for

SCLK_S rising edges greater than 80 when CS_S is active.

3.3.1

SPI pin descriptions

Chip select (CS_D, CS_S)

Chip-select inputs select the device for serial transfers. CS_D or CS_S can be asserted at

any given time and are active low. Both CS_D and CS_S inputs can be selected

simultaneously. When chip-select is asserted, the respective MISO/MISO_S pin is released

from tri-state mode, and all status information is latched into the SPI shift register. While

chip-select is asserted, register data is shifted into MOSI/MOSI_S pin and shifted out of

MISO/MISO_S pin on each subsequent SCLK/ SCLK_S. When chip-select is negated,

MISO/MISO_S pin is tri-stated. To allow sufficient time to reload the registers chip-select pin

shall remain negated for at least tCSN. The chip-select inputs have current sinks which pull

these pins to the negated state when there is an open circuit condition. These pins have

TTL level compatible input voltages allowing proper operation with microprocessors using a

3.3 to 5.0 volt supply.

Serial clock (SCLK, SCLK_S)

SCLK/SCLK_S input is the clock signal input for synchronization of serial data transfer. This

pin has TTL level compatible input voltages allowing proper operation with microprocessors

Table 10. Features that are accessed/controlled for each of the SPIs

Type

Function

Pin names

Features accessed

SPI1

Squib diagnostic & deployment SPI

SCLK

MISO

MOSI

CS_D

All Squib Diagnostics

Squib related status

information Squib Arming

and Firing Software Reset

Component ID & Revision

SPI2

Satellite SPI

SCLK_S

MISO_S

MOSI_S

CS_S

Satellite Channel

Diagnostics

Satellite Communication

Data

Channel Configuration

L9662 Datasheet(PDF) 28 Page - STMicroelectronics

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