L9662 datasheet(37/80 Pages) STMICROELECTRONICS

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L9662

Functional description

High squib resistance diagnostics

During a high squib resistance diagnostic, VRCM and ISINK are switched ON and

connected to SQHx and SQLx on the selected channel. Current flowing on SQHx will be

measured and compared to IHR threshold to identify if resistance is above or below

RSQHZ. The results shall be reported in the next SPI message. Once the command is

issued the state of the squib resistance shall be valid after THSR captured on the next

falling edge of CS_D. The voltage source for this test will be VBIAS which is based on the

VDD supply.

High and low side FET diagnostics

Prior to either the HS or LS FET diagnostics being run it is required to have the VRCM

switched ON. Running the leakage diagnostics with the appropriate delay time prior to either

the HS or LS FET diagnostics will precondition the squib pin to the appropriate voltage level.

When the FET diagnostic command is issued the flags will initially be cleared. Once this is

complete there is a check to determine if the VRCM is not active or some leakage is

present. If either of these conditions are present then the MOS will not be turned ON, the

test will be aborted and the Fault Present (FP) bit will be set. The FEN function must be

inactive for the channel under test in order to be able to run the test. The test will not start if

FEN function is active on the channel under test and will result in the FP bit to be set.

If no leakage is present and FEN function is inactive, the MOS (High side or Low Side) is

turned ON.

The device shall monitor the current sink or sourced by VRCM. If the MOS is working

properly, this current will exceed ISTB (HS test) or ISTG (LS test) and the device shall turn

off the driver under test within the specified time TSHUTOFF. If the current does not exceed

ISTB or ISTG then the test will be terminated and the MOS will be switched off by the ASIC

within TFETTIMEOUT. During the TFETTIMEOUT period the FET Timeout bit will be set

(FT=1) and will be cleared at the expiration of the timer.

The results must be compared with the leakage diagnostic results to distinguish between a

real leakage/short versus a FET fault. For high side FET diagnostics if no faults were

indicated in the preceding leakage diagnostics then a normal result would be STB = 1;

STG = 0 (with FT = 0; FP = 0). If the returned results for the high side FET test is not

STB = 1; STG = 0 (with FT = 0; FP = 0) then either the FET is not functional, a short

occurred during the test, or there is a missing VRESx connection for that channel. For low

side FET diagnostics if no faults were indicated in the preceding leakage diagnostics then a

normal result would be STB = 0; STG = 1 (with FT = 0; FP = 0). If the returned results for the

low side FET test is not STB = 0; STG = 1 (with FT = 0; FP = 0) then either the FET is not

functional, a short occurred during the test, or there is a missing GNDx connection for that

channel.

On the next falling edge of CS_D, comparator results are latched and reported in the MISO

response. The results will remain latched until the next test is initiated (diagnostic write

command). If the test is in progress then a bit is used in the response to indicate the test

completion. If the FET under test is working properly then the results shall indicate a “Short

to Ground” for LS test and “Short to Battery” for HS test.

For all conditions the current on SQHx/SQLx will never exceed ISVRCM. On the squib lines

there will be higher transient currents due to the presence of the filter capacitor.

L9662 Datasheet(PDF) 37 Page - STMicroelectronics

L9662 Datasheet(HTML) 37 Page - STMicroelectronics

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