S7600A datasheet(43/60 Pages) SII

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TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

7-16

7.3.19. Socket Interrupt Mask Low Register (0x2A)

(Read/Write, Default 0x00)

This register reports certain interrupt conditions. Setting a bit enables the corresponding interrupt.

Table 7-33

Socket Interrupt Mask Low Register Bit Definitions

Bit

Def.

TO_En

Buff_

Emp_En

Buff_Full_En

Data_Avail_En

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

Table 7-34

Socket Interrupt Mask Low Register Description

Bit

Bit Name

Access

Description

TO_En

R/W

Writing a “1” enables the Timeout interrupt.

Buff_Empty_En

R/W

Writing a “1” enables the Buffer Empty interrupt.

Buff_Full_En

R/W

Writing a “1” enables the Buffer Full interrupt.

Data_Avail_En

R/W

Writing a “1” enables the Data Available interrupt.

7.3.20. Socket Interrupt Mask High Register (0x2B)

(Read/Write, Default 0x00)

This register enables certain types of interrupt conditions. Setting bits enables their corresponding

interrupts.

Table 7-35

Socket Interrupt Mask High Register Bit Definitions

Bit

Def.

URG_En

RST_En

Term_En

ConU_En

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

Table 7-36

Socket Interrupt Mask High Register Description

Bit

Bit Name

Access

Description

URG_En

R/W

Writing a “1” to enable the Urgent Data interrupt.

RST_En

R/W

Writing a “1” to enable the Connection Reset interrupt.

Term_En

R/W

Writing a “1” to enable the Socket Termination interrupt.

ConU_En

R/W

Writing a “1” to enable the Connection Up interrupt.

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