S7600A datasheet(20/60 Pages) SII

Part #	S7600A

Description	Hardware Specification (TCP/IP Network Stack LSI)

PDF	60 Pages

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Manufacturer	SII [Seiko Instruments Inc]

Direct Link	http://www.sii.co.jp

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20 / 60 page

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

5-3

Seiko Instruments Inc.

5.2.1.2. Read Cycle Timing

Figure 5-2

68k Family MPU Read Timing

Symbol

Description

Min

Max

Notes

TCYC6

System Cycle Time

100 ns

TAH6

Address Hold Time

20ns

TAW6

Address Setup Time

20ns

TDS6

Data Setup time

20ns

TDH6

Data Hold Time

20 ns

TACC6

Access time

30ns

CL=80pF

TOH6

Output Disable Time

20 ns

CL=80pF

TEW

Enable Pulse Width

40 ns

1.9CLK

TBD6

BUSYX Delay Time

30ns

CL=80pF

TBC6

BUSYX Pulse Width

2CLK

TBOD6

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

• CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-4

68k Family MPU Read Cycle Timing

WRITEX

(R/WX)

CLK

BUSYX

READX

(E)

SD7 to 0

TAH6

TDH6

TDS6

TBD6

TBC6

TOH6

TAW6

TAH6

TACC6

TCYC6

TAW6

TAH6

Address

Data

Address

TEW

TBOD

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