TTP255 datasheet(16/49 Pages) TONTEK

16 / 49 page

Preliminary

TTP255

TonTouch

12’/08/21

Page 16 of 49

Ver3.0

Power saving mode condition & Release

Modes

Stop mode

Sleep mode

High speed oscillator

Stopped

Stopped as H/L=0

High speed oscillator

Stopped

Keep Operating

CPU clock

Stopped

CPU internal status

Stop & Retain the status

Memory, Flag, Register,

I/O

Retain the status

Program counter

Hold the next executed address

Peripherals: Time base,

Timers, Interrupts

Stopped & Retain

(Vref off)

Keep Operating

Watch Dog Timer

Disable & cleared

Release Condition

Reset, external INT,

Input wake-up

Reset, external and internal INT

sources, Input Wake-up

S-6: Watch Dog Timer (WDT)

The clock of watch dog timer comes from time base overflow (TB1_1OV). If

time base frequency select 8KHz or 1KHz, watch dog timer’s clock is switch to

64Hz. User can use the time up signal to prevent a software malfunction or

abnormal sequence from jumping to an unknown memory location causing a

system fatal failure. Normally, if the watchdog timer time up signal active that

will reset the chip. At the same time, program and hardware can be initialized

and resume system under normal operation. The chip also provides 2 steps clear

watchdog command as the programmer writes INTAF with $F data first that will

enable the WDT clear, and then writes the power saving (PS) control register

after. Completely finishes the two write & read steps will clear the watch dog

timer. User should well arrange the two command steps for avoiding the dead

lock loop.

User should keep in minds that always reset WDT at main

program and never clear the WDT in the interrupt routine.

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