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TTP255 Datasheet(PDF) 21 Page - Tontek Design Technology

Part # TTP255
Description  Target Spec.
PDF  49 Pages
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Manufacturer  TONTEK [Tontek Design Technology]
Direct Link  http://www.tontek.com.tw
Logo TONTEK - Tontek Design Technology

TTP255 Datasheet(HTML) 21 Page - Tontek Design Technology

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Preliminary
TTP255
TonTouch
TM
12’/08/21
Page 21 of 49
Ver3.0
TCP1F: Timer/counter1 interrupt request flag. (0: inactive; 1: active)
TCP2F: Timer/counter2 interrupt request flag. (0: inactive; 1: active)
TB1_2F: Time base2 2nd interrupt request flag. (0: inactive; 1: active)
INTBF: Interrupt request flag register for CPUB[R/W], default value [0000]
INTF
Bit3
Bit2
Bit1
Bit0
Bit Name
TB2_2F
TCP2F
TCP1F
TB2_1F
Read/Write
R/W
R/W
R/W
R/W
TB2_1F: Time base2 1st interrupt request flag. (0: inactive; 1: active)
TCP1F: Timer/counter1 interrupt request flag. (0: inactive; 1: active)
TCP2F: Timer/counter2 interrupt request flag. (0: inactive; 1: active)
TB2_2F: Time base2 2nd interrupt request flag. (0: inactive; 1: active)
INTAC1: Extended interrupt control register for CPUA [R/W], default value
[0000]
INTC1
Bit3
Bit2
Bit1
Bit0
Bit Name
CPUF2-IEA
CPUF1-IEA
INT1F-IEA
INT0F-IEA
Read/Write
R/W
R/W
R/W
R/W
INT0F-IEA : INT0 external interrupt request enable. (0: disable; 1: enable)
INT1F-IEA : INT1 external interrupt request enable. (0: disable; 1: enable)
CPUF1-IEA : software interrupt1 request enable. (0: disable; 1: enable)
CPUF2-IEA : software interrupt2 request enable. (0: disable; 1: enable)
INTBC1: Extended interrupt control register for CPUB [R/W], default value
[0000]
INTC1
Bit3
Bit2
Bit1
Bit0
Bit Name
CPUF2-IEB
CPUF1-IEB
INT1F-IEB
INT0F-IEB
Read/Write
R/W
R/W
R/W
R/W
INT0F-IEB : INT0 external interrupt request enable. (0: disable; 1: enable)
INT1F-IEB : INT1 external interrupt request enable. (0: disable; 1: enable)
CPUF1-IEB : software interrupt1 request enable. (0: disable; 1: enable)
CPUF2-IEB : software interrupt2 request enable. (0: disable; 1: enable)



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