Electronic Components Datasheet Search
  English  ▼

X  

TTP255 Datasheet(PDF) 18 Page - Tontek Design Technology

Part # TTP255
Description  Target Spec.
PDF  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TONTEK [Tontek Design Technology]
Direct Link  http://www.tontek.com.tw
Logo TONTEK - Tontek Design Technology

TTP255 Datasheet(HTML) 18 Page - Tontek Design Technology

Back Button TTP255 Datasheet HTML 14Page - Tontek Design Technology TTP255 Datasheet HTML 15Page - Tontek Design Technology TTP255 Datasheet HTML 16Page - Tontek Design Technology TTP255 Datasheet HTML 17Page - Tontek Design Technology TTP255 Datasheet HTML 18Page - Tontek Design Technology TTP255 Datasheet HTML 19Page - Tontek Design Technology TTP255 Datasheet HTML 20Page - Tontek Design Technology TTP255 Datasheet HTML 21Page - Tontek Design Technology TTP255 Datasheet HTML 22Page - Tontek Design Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 49 page
background image
Preliminary
TTP255
TonTouch
TM
12’/08/21
Page 18 of 49
Ver3.0
.External Reset (RSTB)
This is one kind of system resetting signal, but only forced externally.
When the chip acknowledged the low level from the pin RSTB exceed 1 us,
it will generate the reset procedure to reset CPU & all the peripheral back
to their initial state (default values).
.Burn out Reset (Program sequence abnormal)
As CPU out of program area, the CPU can detect the abnormal
condition and generate a system reset request.
.Watch Dog Timer Reset
The reset signal will generate automatically when the watchdog timer
runs overflow. If the watchdog timer is cleared regularly by users’ program,
no watchdog reset will occur. Unless the MCU is forced into abnormal state,
the software controlled procedure is disrupted and causing watch dog
timer overflow, then it will generate reset signal to initializes the chip
returning to normal operation.
.Low Voltage Reset (LVR)
The LVR function is used to monitor the supply voltage of MCU, it will
generate a reset signal (with 4*OSCL de-bounce time but no de-bounce in
stop mode) to reset the microcontroller as the VDD power falls below the
default setting level VLVR. It can also be enabled or disabled by
programming “LVREN” bit in PS register.
RESETF: reset source flag register[R/W], power on value [0000]
Register
Bit3
Bit2
Bit1
Bit0
Bit Name
ROMF
BOF
LVRF
WDTF
Read/Write
RW
R/W
R/W
R/W
WDTF: Watch dog timer overflow reset flag (0: no active; 1: active)
LVRF: Low voltage reset flag (0: no active; 1: active)
BOF: Burn out flag(0: no active; 1: active)
ROMF: ROM fail flag(0: no active; 1: active)
(The RESETF is cleared by system reset only)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com