TTP255 datasheet(44/49 Pages) TONTEK

44 / 49 page

Preliminary

TTP255

TonTouch

12’/08/21

Page 44 of 49

Ver3.0

* TT-Bus Status Register 2 (TTSR2), default value [000-]

Bit3

Bit2

Bit1

Bit0

Bit Name

ICF

IAAS

IBB

Read/Write

R/W

ICF – Data Transfer Complete

1(set) – A byte transfer has been completed.

0(clear) – A byte is being transfer.

When ICF is set, the IIF (TT-Bus interrupt) bit is also set. A TT-Bus

interrupt is generated if the IIEN bit is set.

IAAS – Addressed as Slave

1(set) – Currently addressed as slave.

0(clear) – Not currently addressed.

This IAAS bit is set when its own specific address (TT-Bus Address

interrupt) bit is also set. An interrupt is generated if the IIEN bit is set.

Then CPU needs to check the SRW bit and set its TX bit accordingly.

Writing to the TT-Bus Control register 2 clears this bit.

IBB – Bus Busy

1(set) – TT-Bus busy.

0(clear) – TT-Bus idle.

This bit indicates the status of the bus. When a START signal is detected,

IBB is set. When a STOP signal is detected, it is cleared.

* TT-Bus Low Nibble Data I/O Register (TTDRL), default value

[0000]

Bit3

Bit2

Bit1

Bit0

Bit Name

Read/Write

R/W

D3~D0 are the low nibble bits of the TT-Bus module.

In transmit mode, data written into this register is sent to the bus

automatically, with the most significant bit out first. In receive mode,

reading of this register initiates receiving of the next byte data.

* TT-Bus High Nibble Data I/O Register (TTDRH), default value

[0000]

Bit3

Bit2

Bit1

Bit0

Bit Name

Read/Write

R/W

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