CS98000 datasheet(41/46 Pages) CIRRUS

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CS98000

6.4

ROM/NVRAM Interface

This is the interface to the non-volatile memory

that contains the firmware. See Table 19. It could

be either ROM, NVRAM – FLASH, or EEPROM,

or any combination of these types of memory. This

interface can also connect to SRAM that would em-

ulate a ROM on a development system. The bus

width is 8 or 16 bits. Except for the NVM_WE_N

and NVM_OE_N pins, all these pins are shared

with the DRAM interface, which operates simulta-

neously with the ROM/NVRAM interface.

6.5

Video Output Interface

This is the interface to a video encoder chip that

will send the CS98000 video signals to a TV. See

Figure 20. The output format is either CCIR-601 or

CCIR-656. The CS98000 supports both master and

slave configuration. For CCIR-656 mode, the

CS98000 must be the sync master. In this case, the

HSYNC and VSYNC pins can be redefined as

GPIOs

Signal Name

Type

Description

60, 56, 54, 49,

46, 44, 40, 33,

37, 42, 45, 48,

51, 55, 59. 62

M_D[15..0]

Memory Data Bus. Use M_D[7:0] for 8-bit interface

2, 3, 5, 6, 7, 9,

10, 11, 13, 14,

15, 16

M_A[11..0]

Memory Address Bus[11..0]

74, 71, 68, 64,

67, 70, 72, 75,

78, 80, 86, 88

M_D[27..16]

Memory Address Bus[23..12]

For

16-bit data mode, M_D[26:16] is upper word address.

For 8-bit data mode, M_D[27:16] is upper byte address.

M_D[30]

Address decode low. Copy of address MSB.

M_D[31]

Address decode high. Compliment of address MSB.

NVM_WE_N

NVRAM Write Enable.

NVM_OE_N

ROM/NVRAM Output Enable.

Table 19. ROM/NVRAM Interface

Signal Name

Type

Description

154

CLK27_O

27 Mhz Clock Output.

159

HSYNC

Horizontal Sync. Output when the CS98000 is the video

master, input when the video encoder is master.

162

VSYNC

Vertical Sync. Output when the CS98000 is the video mas-

ter, input when the video encoder is master.

173, 172, 170,

169, 167, 166,

165, 163

VDAT[7..0]

Video Data Output[7..0] in Cb,Y,Cr,Y format.

Table 20. Video Output Interface

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