AD6635 datasheet(31/60 Pages) AD

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AD6635

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Table VI. Output Mode Formats

Floating Point 12 + 4

Floating Point 8 + 4

Fixed Point

Normally, the AD6635 will determine the exponent value that

optimizes numerical accuracy. However, if Bit 6 of this control

output. This ensures that consistent scaling and accuracy dur-

ing conditions that may warrant predictable output ranges. If

Bits 3–0 are represented by RCF Scale, then the scaling factor in

dB is given by:

Scaling Factor = RCF Scale – 3

()¥

()

log

For RCF Scale of 0, the Scaling Factor is equal to

–18.06 dB, and for maximum RCF Scale of 15, the Scaling

Factor is equal to 72.25 dB.

If Bit 7 of this register is set, the same exponent will be used for

both the real and imaginary (I and Q) outputs. The exponent

used will be the one that prevents numeric overflow at the

expense of small signal accuracy. However, this is seldom a

problem, as small numbers would represent 0 regardless of

the exponent used.

Bit 8 of this register is the RCF bank select bit used to program

the register. When this bit is 0, the lowest block of 128 is selected

(taps 0 through 127). When high, the highest block is selected

(taps 128 through 255). It should be noted that while the chip

is computing filters, tap 127 is adjacent to 128 and there are no

paging issues.

Bit 9 of this register selects where the input to each RCF comes

from. If Bit 9 is clear, the RCF input comes from the CIC5

normally associated with the RCF. For Channels 0 through 3, if

the bit is set, the input comes from CIC5 Channel 1. The only

exception is Channel 1, which uses the output of CIC5 from

Channel 0 as its alternate. Using this feature, each RCF can

operate either on its own channel’s NCO + rCIC2 + CIC5 data

or be paired with the RCF of Channel 1. The RCF of Channel 1

can also be paired with Channel 0. This control bit is used with

polyphase distributed filtering.

Similarly for Channels 4 through 7, if the bit is set, the input

comes from CIC5 Channel 5. The only exception is Channel 5,

which uses the output of CIC5 Channel 4 as its alternate source.

If Bit 10 is clear, the AD6635 channel operates in normal

mode. However, if Bit 10 is set, then the RCF is bypassed to

perform Channel BIST. See the Channel BIST (Built-in Self

Test) section below for more details.

Note that the outputs of the RCF can be sent directly to the

output ports (parallel or link) using the appropriate setting in

Port Control register (see Memory Map for Output Port Con-

trol Registers). Alternately, data from more than one channel

can be interleaved into the interpolating half-band filters and

AGCs (even if half-band filters and AGCs are bypassed, inter-

leaving function is still accomplished). This feature to interleave

data internal to the AD6635 allows the usage of multiple chan-

nels to process a single carrier.

Although this data must be written in pages, the internal core

handles filters that exceed the length of 128 taps. Therefore, the

full length of the data RAM may be used as the filter length

(160 taps). Though the RCF can calculate only 160 tap filters,

the filter coefficient memory is 256 words long so that more

than one filter configuration can be stored in the memory, and

can be selected using the Coefficient Offset 0xA3 register.

The RCF stores the data from the CIC5 into a 160

¥ 40 RAM.

160

¥ 20 is assigned to I data, and 160 ¥ 20 is assigned to Q

data. The RCF uses the RAM as a circular buffer so that it is

difficult to know in which address a particular data element is

stored. To avoid start-up transients due to undefined data RAM

values, the data RAM should be cleared upon initialization.

When the RCF is triggered to calculate a filter output, it starts

by multiplying the oldest value in the data RAM by the first

coefficient, which is pointed to by the RCF Coefficient Offset

newer data-words multiplied by the subsequent locations in the

coefficient RAM until the coefficient address RCFOFF + NTAPS – 1

is reached.

Table V. Three-Tap Filter

Coefficient Address

Impulse Response

Data

h(0)

N(0) oldest

h(1)

N(1)

2 = (NTAPS – 1)

h(2)

N(2) newest

The RCF Coefficient Offset register can be used for two pur-

poses. The main purpose of this register is allow for multiple

filters to be loaded into memory and selected simply by chang-

ing the offset as a pointer for rapid filter changes. The other use

of this register is to form part of symbol timing adjustment. If

the desired filter length is padded with zeros on the ends, the

starting point can be adjusted to form slight delays in when the

filter is computed with reference to the high speed clock. This

allows for vernier adjustment of the symbol timing. Course

adjustments can be made with the RCF Decimation Phase.

The output rate of this filter is determined by the output rate of

the CIC5 stage and MRCF:

SAMPR

SAMP

RCF

RCF Output Scale Factor and Control Register

several aspects of the RCF register. Bits 3–0 are used to set the

scale of the fixed-point output mode. This scale value may also

be used to set the floating-point outputs in conjunction with

Bit 6 of this register.

Bits 4 and 5 determine the output mode. Mode 00 sets the chip

up in fixed-point mode. The number of bits is determined by

the parallel or link port configuration.

Mode 01 selects floating-point mode 8 + 4. In this mode, an

8-bit mantissa is followed by a 4-bit exponent. In mode 1x (x

is don’t care), the mode is 12 + 4, or 12-bit mantissa and 4-bit

exponent.

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